Method of fabricating mask ROM

Details Method of fabricating mask ROM Method of fabricating mask ROM

2002-12-18

2004-03-23

Ho, Hoai (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06709933

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a mask ROM, in particular, for allowing a flat cell type mask ROM to be applied to both a dual gate process and a salicide process in use for a logic process.
2. Description of the Prior Art
As generally known in the art, a mask ROM is a type of non-volatile device. A mask process is applied to fabrication of the mask ROM such as a device isolation process, a metal process and an ion injection process in respect to a channel region of a memory cell. Referring to the ion injection process, a first memory cell through the ion injection process has a threshold voltage which is different from that of a second memory cell which has not undergone the ion injection process. The difference of the threshold voltages is used to judge data and write necessary information.
FIG. 1
shows a layout of a general cell array.
Flat cell type mask ROMs as shown in
FIG. 1
are most common ROMs fabricated according to a logic process.
As shown in
FIG. 1
, fabrication of the above flat cell type mask ROM carries out an isolation process around a memory cell array region
10
to have a structure for surrounding the entire memory cell array region
10
without separate Local Oxidation of Silicon (LOCOS) or Shallow Trench Isolation (STI). Source/drain junctions are a buried layer
116
which is formed before a gate-forming process. It is unnecessary to separate the junctions. A contact hole
150
for the buried layers or junctions exists only in a segment select region
20
, not in a memory cell array region
10
. Also, gates
126
are formed perpendicular to the buried layers or junctions, and have a width corresponding to a channel width of the memory cell.
Since the flat cell type mask ROM does not have an isolation pattern or contact hole in the memory cell as explained above, high integration can be realized owing to memory cell size of 4F2 (F means the minimum line width of photolithography). Also a fabricating process is simplified and fabrication cost is saved.
Where fabrication of the flat cell type mask ROM having the above advantages utilizes a logic process using a design rule of 0.35 &mgr;m or more, 1) an isolation process is performed via LOCOS; 2) available examples of gate-forming materials include poly crystalline silicon doped with N-type impurities and Ti-salicide or W-polycide; and 3) the source/drain junctions are made of Ti-salicide, which is used as a gate-forming material.
Further, where fabrication of the flat cell type mask ROM utilizes a logic process using a design rule of 0.25 &mgr;m or less, 1) an isolation process is performed in a manner that the entire memory cell array regions are surrounded by a trench STI; 2) available examples of gate-forming materials include Ti-salicide and Co-salicide; and 3) the source/drain junctions are made of Ti-salicide or Co-salicide, which is used as a gate-forming material.
A flat cell type mask ROM compatible with the logic process having the design rule of 0.35 &mgr;m or more has been commercialized up to the present, whereas a process of fabricating a flat cell compatible with the logic process having the design rule of 0.25 &mgr;m or less has not been developed. Therefore, it is urgent to pursue research about the logic process having the design rule of 0.25 &mgr;m or less.
As shown in
FIG. 2
, a conventional method of fabricating a mask ROM comprises the steps of: forming a device isolation film in a peripheral portion of a memory cell array region; forming a well; forming a buried layer; forming a gate insulation film and gate regions in the memory cell array region and a peripheral region; injecting cell-isolating ion into the memory cell array region; forming source/drain regions in the gates of the peripheral region, performing a coding; forming a contact hole in the buried layer of a segment select region; and forming bit lines.
FIGS. 3A and 3G
are sectional views along A-B-C line in
FIG. 1
, illustrating a conventional process of fabricating a mask ROM. In
FIGS. 3A
to
3
G, a region I indicates a cell which is taken horizontal to the gates (i.e., along A-B line), and regions II and III indicate the cell which is taken perpendicular to the gates (i.e., along B-C line).
As shown in
FIG. 3A
, the conventional process of fabricating a mask ROM primarily prepares a substrate
100
defined by a memory cell array region I and II and a peripheral region III.
Then, a device isolation film
103
is formed in a peripheral portion of the memory cell array region I and II of the substrate
100
via LOCOS or STI.
Ion injection is performed to the resultant substrate
100
and the device isolation film
103
, thereby forming a well
102
. Alternatively, the device isolation film
103
can be formed before the well
102
.
AS shown in
FIG. 3B
, a photosensitive film is applied to the surface of the resultant substrate having the device isolation film
103
and the well
102
. Then, the photosensitive film is exposed and developed to form a first photosensitive film pattern
104
for opening predetermined regions. A buffer oxide film
105
is interposed between the first photosensitive film pattern
104
and the substrate
100
.
In sequence, using the first photosensitive film pattern
104
as a mask, N-type As
+
ion injection
106
is performed to the entire surface of the substrate having the device isolation film
103
and the well
102
, thereby forming an As
+
ion layer
108
.
As shown in
FIG. 3C
, after removing the first photosensitive film pattern, heat treatment is performed to the substrate having the As
+
ion layer, thereby forming a buried layer
116
via As
+
ion dispersion. Simultaneous with the formation of the buried layer
116
, an insulation film
112
such as a native oxide film is formed overlying the buried layer
116
.
Then, a silicon oxide film
112
and a gate-forming material layer
125
are sequentially formed on the entire surface of the substrate having the buried layer
16
and the insulation film
112
. The gate-forming material layer
125
utilizes a polycrystalline silicon layer doped with impurities or an amorphous silicon layer doped with impurities and a salicide-forming metal layer overlying the selected silicon layer. The metal layer is made of one selected from a group including Ti, Co, Pt and Ni.
As shown in
FIG. 3D
, a second photosensitive film pattern
134
is so formed on the resultant substrate to cover the entire region of the peripheral region III and a gate-forming region of the memory array region I and II. Then, using the second photosensitive film pattern
134
as a mask, the gate-forming material layer and the silicon oxide film are dry-etched, thereby forming a gate insulation film
123
and gates
126
in the memory cell array region I and II. Where the gate-forming material layer is etched, each of exposed silicon regions
128
in the substrate corresponds to each of intervals of memory cell channels.
Using the second photosensitive film pattern
134
as a mask, ion injection
132
for cell isolation is performed to the intervals
128
of the channels of the memory cell array region I and II.
As shown in
FIG. 3E
, after removing the second photosensitive film pattern, a BPSG protective film
130
is deposited on the substrate, which underwent the ion injection, thereby filling spaces between the gates
126
of the memory cell. Then, the protective film
130
undergoes etchback or Chemical Mechanical Polishing (CMP), thereby planarizing the surface of the resultant substrate.
Then, as shown in
FIG. 3F
, a third photosensitive film pattern
136
is formed on the substrate having the protective film
130
to cover the entire memory cell array region I and II and the gate-forming region of the peripheral region III.
Using the third photosensitive film pattern
136
as a mask, the silicon oxide film and the gate material layer in the peripheral region III are dry-etched, thereby forming a gate insulation film
123
and gates
126
.
Then, using the th

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