Method of fabricating mask read only memory

Details Method of fabricating mask read only memory Method of fabricating mask read only memory

2001-08-14

2002-10-22

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S275000, C438S276000, C438S277000

Reexamination Certificate

active

06468869

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90111227, filed May 11, 2001.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a method of fabricating a mask read only memory (ROM). More particularly, the invention relates to a method of fabricating a mask read only memory used to store two bits in one memory unit in programming.
2. Description of the Related Art
Due to the non-volatile property that avoids memory loss by power interruption, many electric products require read only memories to maintain normal operation between on and off. That mask read only memory is one of the basic read only memories. The commonly used mask read only memory uses a channel transistor as a memory cell. An ion implantation step is performed on the selected channels in programming, and the on or off state of the memory cell is controlled by changing the threshold voltage. In the structure of the mask read only memory, the polysilicon word line (WL) is formed across the bit line (BL). The channel regions of the memory cells are formed under the word line between the bit line. Whether the channel is implanted with ions determines which of the two-bit data “0” and “1” is stored. The step of implanting ions into the selected channel regions is called the “code implantation process”.
FIG. 1
shows a top view of a conventional mask read only memory. In
FIG. 1
, the parallel bit lines
102
run across the parallel bit lines
104
. The ion implantation block
110
of the substrate, that is, the channel region of the memory cell, is implanted with ions for programming. The threshold voltage is thus altered to achieve the objective of controlling on/off of the memory cell.
FIG. 2
shows a cross-sectional view of the conventional mask read only memory. A plurality of gate stacked structures
206
, each of which comprises a gate dielectric layer
202
and a gate conductive layer
204
, is formed on a substrate
200
. A source/drain region
208
is formed in the substrate
200
between the gate stacked structures
206
. A dielectric layer
210
is formed to cover the gate stacked structures
206
. While performing the implantation coding process, a patterned photoresist layer
212
is formed using a photomask to expose the region to be coded. An ion implantation
214
is then performed using the photoresist layer
212
as a mask. Boron ions are implanted into the substrate
200
at a bottom of the coding area under the stacked gate structures
206
to perform programming, so that the program is coded in the read only memory.
During the ion implantation step for programming, boron ions are implanted into the substrate
200
by penetrating through the gate stacked structure
206
. A large implantation energy is thus required. Using a large energy to implant boron ions requires a large thermal budget for the device. It is thus easy to cause ion scattering or diffusion towards other positions of the substratewhich interferes with control of the device. As the integration of integrated circuit increases, and the production of the mask read only memory has reached the sub-micron process, the dimension of devices decreases. Consequently, interference with control is more significant.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating a mask read only memory to store a two bit data in one memory unit with an increased integration. Without increasing the number of photomasks, the mask read only memory is fabricated with a higher density.
The method of fabricating a mask read only memory provided by the invention also resolves the interference problem, caused by ion scattering and diffusion in the substrate, by using a reduced implantation energy.
In the above method of fabricating a mask read only memory, a plurality of gate stacked structures, each of which comprises a gate dielectric layer, a gate conductive layer and a gate cap layer, is formed on a substrate. A plurality of source/drain regions is formed in the substrate between the gate stacked structures, while the source/drain regions are not adjacent thereto. Regions of the substrate between the source/drain regions and the gate stacked structures are defined as the coding areas. A first dielectric layer is formed to fill spaces between the gate stacked structures. A photoresist layer with a plurality openings exposing the first dielectric layer on the coding areas is formed. Using the photoresist layer as a mask, the exposed first dielectric layer is removed to form a plurality of implantation openings of the coding areas. An ion implantation step is performed on the exposed coding areas to form a plurality coding implanted blocks. The photoresist layer is removed, and a second dielectric layer is formed to fill the implantation openings. An etching back process is performed to expose the gate conductive layer. A word line is formed on the gate conductive layer.
In the above methods, spacers are formed on sidewalls of the gate stacked structures, such that small channels are formed in the substrate between the source/drain regions and the gate conductive layers. Different forms of dopants are then used to connect or cut off the small channels for data loading. Thus, two bits of data can be stored in one memory cell to enhance the integration. The same number of photomasks is used to fabricate a mask read only memory with an increased density.
In addition, one conductive layer may also be formed on the source/drain regions to reduce the resistance of the source/drain regions, so as to improve the device performance.
In the coding implantation step, the ions are implanted into the substrate between gate conductive layers and the source/drain regions directly, so that the implantation energy is reduced. The interference problems caused by ions scattering and diffusion problems occurring to the conventional method can thus be resolved.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 5278078 (1994-01-01), Kanebako et al.
patent: 5407852 (1995-04-01), Ghio et al.
patent: 6030871 (2000-02-01), Eitan
patent: 6133101 (2000-10-01), Wu

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