Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into...
Reexamination Certificate
2007-10-02
2007-10-02
Lebentritt, Michael (Department: 2812)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
C438S511000, C438S199000, C438S302000, C438S305000, C438S306000, C438S307000, C438S217000, C438S224000, C438S512000, C438S513000, C438S514000, C438S515000, C438S516000, C438S517000, C438S518000, C438S519000, C438S520000, C438S521000, C438S522000, C438S523000, C257S492000, C257S493000, C257SE21087
Reexamination Certificate
active
11067212
ABSTRACT:
An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.
REFERENCES:
patent: 3891469 (1975-06-01), Moriyama et al.
patent: 4466178 (1984-08-01), Soclof
patent: 4987093 (1991-01-01), Teng et al.
patent: 5019520 (1991-05-01), Komori et al.
patent: 5055417 (1991-10-01), Akcasu
patent: 5108783 (1992-04-01), Tanigawa et al.
patent: 5160996 (1992-11-01), Odanaka
patent: 5286995 (1994-02-01), Malhi
patent: 5420061 (1995-05-01), Manning
patent: 5478759 (1995-12-01), Mametani et al.
patent: 5478761 (1995-12-01), Komori et al.
patent: 5501993 (1996-03-01), Borland
patent: 5569620 (1996-10-01), Linn et al.
patent: 5573963 (1996-11-01), Sung
patent: 5643822 (1997-07-01), Furukawa et al.
patent: 5668755 (1997-09-01), Hidaka
patent: 5693505 (1997-12-01), Kobayashi
patent: 5698458 (1997-12-01), Hsue et al.
patent: 5798295 (1998-08-01), Hoover et al.
patent: 5811334 (1998-09-01), Buller et al.
patent: 5817546 (1998-10-01), Ferla et al.
patent: 5898007 (1999-04-01), Lee
patent: 5930642 (1999-07-01), Moore et al.
patent: 5966599 (1999-10-01), Walker et al.
patent: 6017787 (2000-01-01), Chittipeddi et al.
patent: 6054374 (2000-04-01), Gardner et al.
patent: 6072216 (2000-06-01), Williams et al.
patent: 6096625 (2000-08-01), Daniel et al.
patent: 6177333 (2001-01-01), Rhodes
patent: 6184557 (2001-02-01), Poplevine et al.
patent: 6251757 (2001-06-01), Yu
patent: 6297119 (2001-10-01), Tsutsui et al.
patent: 6359317 (2002-03-01), Carroll et al.
patent: 6365447 (2002-04-01), H'ebert et al.
patent: 6391700 (2002-05-01), Tsay
patent: 6391754 (2002-05-01), Paranjpe
patent: 6406974 (2002-06-01), Wu et al.
patent: 6413827 (2002-07-01), Farrar
patent: 6476457 (2002-11-01), Oh
patent: 6495896 (2002-12-01), Yaegashi et al.
patent: 6501131 (2002-12-01), Divakaruni et al.
patent: 6586297 (2003-07-01), U'Ren et al.
patent: 6599782 (2003-07-01), Kikuchi
patent: 6617217 (2003-09-01), Nandakumar et al.
patent: 6630699 (2003-10-01), Wylie
patent: 6885080 (2005-04-01), Chen et al.
patent: 6897520 (2005-05-01), Vora
patent: 6900091 (2005-05-01), Williams et al.
patent: 2002/0098638 (2002-07-01), Yaegashi et al.
patent: 2004/0259318 (2004-12-01), Williams et al.
patent: 2005/0014324 (2005-01-01), Williams et al.
patent: 2005/0014329 (2005-01-01), Williams et al.
patent: 2005/0142791 (2005-06-01), Williams et al.
patent: 2005/0142792 (2005-06-01), Williams et al.
patent: 2005/0158939 (2005-07-01), Williams et al.
patent: 2006/0223257 (2006-10-01), Williams et al.
patent: 1357598 (2003-10-01), None
patent: 2320812 (1998-07-01), None
patent: 2000 11436 (2000-04-01), None
patent: WO 02/052649 (2002-07-01), None
patent: WO 03/054950 (2003-07-01), None
Contiero et al., “LDMOS Implemenatation By Large Tilt Implant In 0.6 μm BCD5 Process, Flash Memory Compatible,” IEEE (1996) pp. 75-78.
Kurol et al., “Bipolar Transistor with a Buried Layer Formed by High-Energy Ion Implantation for Subhalf-Micron Bipolar-Complementary Metal Oxide Semiconductor LSls,” Jpn. J. Appl. Phys., vol. 33 (1994) No. 1B, Jan. 1994, pp. 541-545.
Chan Wai Tien
Cornell Michael E.
Williams Richard K.
Advanced Analogic Technologies (Hong Kong) Limited
Advanced Analogic Technologies, Inc.
Ahmadi Mohsen
Lebentritt Michael
Steuber David E.
LandOfFree
Method of fabricating isolated semiconductor devices in... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating isolated semiconductor devices in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating isolated semiconductor devices in... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3827283