Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Polycrystalline semiconductor
Reexamination Certificate
1999-08-20
2001-02-27
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
Polycrystalline semiconductor
C438S478000, C438S964000
Reexamination Certificate
active
06194292
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention generally relates to semiconductor devices and methods of manufacture, and more particularly to a method of fabricating in-situ doped, rough polycrystalline silicon using a single wafer reactor.
BACKGROUND OF THE INVENTION
As semiconductor memory device dimensions continue to shrink, and the corresponding density continues to increase by a 4× rule, the storage cell gets increasingly smaller while the required storage charge remains about the same. Conventional oxynitride (N/O or O/N/O) dielectrics have a relatively low capacitance per unit area (~7.7 fF/um2, for an effective oxide thickness of 4.5 nm) that limits the storage capacity because of high tunneling leakage. To combat this problem, various area enhancement technique have been proposed, including hemispherical grain (HSG) or rough polysilicon film growth techniques, and disk, fin, and corrugated cylindrical cell (CCC) cell structures.
Storage cells that incorporate fins, disks, and CCC formations are primarily composed of multiple horizontal fins to add surface area. However, as the storage cell size is further decreased, the horizontal fins add less surface area than vertical sidewalls. Furthermore, the typical fin-type structure is a less robust structure that can more easily sustain damage during processing, especially during oxide and particle removal between the fins.
Storage cells incorporating roughened polysilicon have been proposed using thin film growth techniques including HSG, ion implementation, and native oxide promoted rough polysilicon growth. Little or no leakage penalty has been identified for the rough storage polysilicon cell structures as compared to the smooth polysilicon structures. However, these growth techniques involve depositing the rough polysilicon onto undoped polysilicon. Therefore, additional doping is required to avoid interfacial depletion, introducing a low capacitance layer coupled with N/O thin dielectrics. The HSG technique typically further requires multiple complex deposition and annealing steps performed within a relatively narrow deposition temperature window (less than or equal to about 5° C.). The rough polysilicon technique typically further requires native oxide as a base in order to form rough surfaces. In addition, currently, deposition of rough polycrystalline silicon is done in a vertical furnace and results in non-uniform deposition across a wafer and from wafer to wafer in a whole wafer load, i.e., approximately 100 wafers. Therefore, conventional HSG and rough polysilicon formation techniques do not provide a robust technology for manufacturing. As a result, a storage cell grown using conventional HSG or rough polysilicon techniques typically lacks desired mechanical strength and stability.
Gas phase nucleation has been used as a growth technique to deposit GaAs clusters for formation of quantum dots. Controlling the gas phase nucleation enables control of sizes of gas phase nucleated particles and surface morphology. A detailed description of gas phase nucleation kinetics is provided in the following references: “Gas-Phase Nucleation in GaAs Thin Film Preparation by Metal Organic Chemical Vapor Deposition,” K. Okuyama, D. D. Huang, J. H. Seinfeld, N. Tani, and I. Mansui, Japan Journal of Applied Physics, Volume 31, pp 1-11 (1992); and “Lower-Dimensional Quantum Structures by Selective Growth and Gas-Phase Nucleation,” K. J. Vahala, W. A. Saunders, C. S. Tsai, P. C. Sercel, T. Kuech, H. A. Atwater, and R. C. Flagan, Journal of Vacuum Science Technology, B11, 1660 (1993). Gas phase nucleation has typically been avoided in deposition of polysilicon due to resulting rough structure and particulate generation during the gas phase.
SUMMARY OF THE INVENTION
The present invention provides a method of fabricating polycrystalline silicon for use in a semiconductor memory device storage device that substantially eliminates or reduces disadvantages and problems associated with previously developed fabrication techniques.
More specifically, the present invention provides a method for fabricating polycrystalline silicon for use in a semiconductor memory device storage cell structure having an increased surface area. The method of the present invention is advantageously performed using a single process in a single wafer reactor under conditions that result in nucleation and growth of rough polycrystalline silicon. The method for forming rugged polycrystalline silicon comprises depositing in-situ doped rugged polycrystalline silicon on a substrate in a single wafer chemical vapor deposition chamber under predetermined temperature conditions and predetermined pressure conditions that result in nucleation and growth of a rugged polycrystalline silicon. The deposition comprises substantially simultaneously flowing SiH
4
, PH
3
and H
2
into the single wafer reactor.
The present invention provides a technical advantage by increasing the surface area of a storage cell that employs the rough polycrystalline silicon. The method thereby increases the total capacitance per storage cell. The total capacitance of a storage cell using polycrystalline silicon fabricated using the method of the present invention can have two or more times the capacitance of a storage cell with smooth polysilicon surfaces.
The present invention provides another technical advantage in the use of a single wafer reactor that enables more precise control of the deposition conditions such as temperature, pressure and gas flow as compared to the furnace type reactor that is typically used to deposit rough polycrystalline silicon. The use of a single wafer reactor also improves deposition thickness uniformity from wafer to wafer as compared to the use of a furnace type reactor. Further, deposition takes place in a single step thus simplifying fabrication.
REFERENCES:
patent: 5080933 (1992-01-01), Grupen-Shemansky
patent: 5607724 (1997-03-01), Beinglass et al.
patent: 5783257 (1998-07-01), Shishiguchi et al.
patent: 5863598 (1999-01-01), Venkatesan et al.
Ando Toshio
Aoyama Shintaro
Tsu Robert Yung-Hsi
Brady III W. James
Elms Richard
McLarty Peter K.
Smith Bradley K
Telecky , Jr. Frederick J.
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