Method of fabricating high voltage semiconductor device

Details Method of fabricating high voltage semiconductor device Method of fabricating high voltage semiconductor device

1998-10-30

2001-01-30

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S305000, C438S525000, C438S529000

Reexamination Certificate

active

06180471

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority benefit of Taiwan application Ser. No. 87113699, filed Aug. 20, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method of fabricating a high voltage semiconductor, and more particularly to a method of fabricating a lightly doped drain (LDD) in a semiconductor device.
2. Description of the Related Art
The modern integrated circuit techniques is developed towards the direction of narrower line width and shorter channel length of a metal oxide semiconductor (MOS). By applying a constant voltage, the lateral electric field in the channel is increased as reducing the channel length. Thus, the electron in the channel is accelerated, and the energy of the electron is increased, especially in the vicinity between the channel and the source/drain region. The energy of the electron is higher than the energy of an electron under thermal equilibrium. Some of the electron in the channel tunnels through the oxide layer. Therefore, the produced hole flows into the substrate, and a leakage current occurs.
To reduce the hot electron effect, a lightly doping process is performed at the vicinity between the source/drain region and the channel before the formation of a heavily doped source/drain region. An LDD structure is formed, and the leakage current is prevented.
Referring to
FIG. 1A
to
FIG. 1E
, cross sectional views of an LDD structure in a MOS is shown.
Referring to
FIG. 1A
, on a P-type semiconductor substrate
1
, an oxide layer
2
is formed. On the oxide layer, a conductive layer
2
is formed. After patterning, a gate
4
is formed. The formation of the oxide layer
2
is to moderate the scattering of subsequent implanted ions due to collision with the silicon atoms of the substrate in an amorphous form. The diffusion of ions into the P-type semiconductor substrate is thus avoided.
Referring to
FIG. 1B
, N
−
ions are implanted with an angle of about 0° to 7° towards the semiconductor substrate
1
to form a lightly doped region
6
and
8
. The implantation ions are, for example, phosphorous ions (P
31
) having a concentration of 1×10
13
/cm
2
to 1×10
14
/cm
2
with an energy between 30 KeV to 100 KeV. The resultant implantation depth is about 0.02 &mgr;m to
0.15 &mgr;m.
Referring to
FIG. 1C
, using thermal drive-in, the implantation depth of the lightly doped region
6
and
8
is extended from to 0.25 &mgr;m to 0.6 &mgr;m as a lightly doped region
6
a
and
8
a.
The thermal drive-in is performed at about 850° C. to 1050° C.
Referring to
FIG. 1D
, a silicon oxide layer is formed and defined to form a spacer
10
on s side wall of the gate.
Referring to
FIG. 1E
, using the gate
2
and the spacer
10
as masks, ion implantation is performed with heavy N
+
ions at an angle of about 0° to 7° to form a heavily doped region
6
b
and
8
b.
The implantation ions are, for example, phosphorous or arsenic ions with a concentration of about 1×10
14
/cm
2
to 1×10
15
/cm
2
at an energy about 100 KeV to 200 KeV.
In the convention method of fabricating a high voltage semiconductor, an LDD source/drain structure is formed after the formation of gate. A lightly ion implantation is performed to form a lightly doped region. By thermal drive-in, the implantation depth of the lightly doped region is extended. After the formation of a spacer, a heavy doped region is formed within the lightly doped region by ion implantation. Using the gate as a mask to perform ion implantation, the concentration of dopant within the gate is altered, and therefore, the characteristics of the device, such as the threshold voltage, are altered. Moreover, during the thermal drive-in process, a cross diffusion occurs between the gate and the lightly doped region. Thus, the device is degraded. The degradation is further obvious for the sub-micron process.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a method of fabricating a high voltage semiconductor device. An oxide layer is formed on the gate before ion implantation for forming a lightly doped region to protect the gate from being further doped and damaged. Therefore, the concentration of dopant within the gate is not altered. Moreover, ion implantation is performed with a wide angle. The thermal drive-in process is not necessary to performed. The cross diffusion of the dopant between the doped region within the substrate and gate is avoid. The reliability of the device is enhanced.
To achieve these objects and advantages, and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed towards a method of fabricating a high voltage semiconductor device. A semiconductor substrate doped with a first type dopant and comprising a gate is provided. A cap oxide layer is formed on the gate optionally. A first ion implantation with a light second type dopant at a wide angle is performed to form a lightly doped region. A spacer is formed on a side wall of the gate. A second ion implantation with a heavy second type dopant is performed, so that a heavily doped region is formed within the lightly doped region.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 5376566 (1994-12-01), Gonzalez
patent: 5518941 (1996-05-01), Lin et al.
patent: 5753556 (1998-05-01), Katada et al.
patent: 5770502 (1998-06-01), Lee
patent: 5834347 (1998-11-01), Fukatsu et al.
patent: 5966604 (1999-10-01), Lin et al.
patent: 6020228 (2000-02-01), Asakura

Affiliated with

Also associated with

Rating

Method of fabricating high voltage semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating high voltage semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating high voltage semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2447191