Method of fabricating high-voltage MOS device

Details Method of fabricating high-voltage MOS device Method of fabricating high-voltage MOS device

2007-05-08

2007-05-08

Smith, Zandra V. (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S217000, C438S289000, C438S450000

Reexamination Certificate

active

10908917

ABSTRACT:
A HV-MOS device is described, including a substrate, a gate dielectric layer and a gate, a channel region, two doped regions as a source and a drain, a field isolation layer between the gate and at least one of the two doped regions, a drift region and a modifying doped region. The drift region is located in the substrate under the field isolation layer and connects with the channel region and the at least one doped region. The modifying doped region is at the periphery of the at least one doped region.

REFERENCES:
patent: 5650658 (1997-07-01), Beasom
patent: 5716886 (1998-02-01), Wen
patent: 5747850 (1998-05-01), Mei
patent: 6144538 (2000-11-01), Chao
patent: 6214674 (2001-04-01), Tung
patent: 6306700 (2001-10-01), Yang
patent: 6333234 (2001-12-01), Liu

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