Method of fabricating high voltage metal oxide semiconductor...

Details Method of fabricating high voltage metal oxide semiconductor... Method of fabricating high voltage metal oxide semiconductor...

2007-10-11

2008-12-09

Weiss, Howard (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S213000, C438S216000, C257S491000, C257S492000

Reexamination Certificate

active

07462532

ABSTRACT:
A high voltage metal oxide semiconductor device comprising a substrate, an N-type epitaxial layer, an isolation structure, a gate dielectric layer, a gate, an N-type drain region, a P-type well, an N-type source region, a first N-type well and a buried N-doped region is provided. The first N-type well is disposed in the N-type epitaxial layer under the isolation structure and on one side of the gate. The first N-type well overlaps with the N-type drain region. The buried N-doped region is disposed in the substrate under the N-type epitaxial layer and connected to the first N-type well.

REFERENCES:
patent: 5539238 (1996-07-01), Malhi
patent: 6265752 (2001-07-01), Liu et al.
patent: 2004/0195644 (2004-10-01), Mallikarjunaswamy et al.

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