Method of fabricating high density flat cell mask ROM

Details Method of fabricating high density flat cell mask ROM Method of fabricating high density flat cell mask ROM

1996-06-04

1997-09-16

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

H01L 2170

Patent

active

056680317

ABSTRACT:
A method of fabricating a high density flat mask read only memory. At first a plurality of trenches are formed in a surface of a silicon substrate at predetermined desired source-drain electrodes areas. A dielectric layer is formed on at least the surface of the trenches. A first polysilicon layer is formed over the dielectric layer and then portions of the first polysilicon layer are removed to leave a portion thereof on the bottom of each trench. Using the first polysilicon layer as an etch stop layer, the dielectric layer is etched. A second polysilicon layer then is formed on the surface of the silicon substrate, the first polysilicon layer and the dielectric layer, and then the the second polysilicon layer is etched back to the substrate surface to form the source-drain electrode areas, that is, the bit lines. On the surface of the bit lines and the silicon substrate, a gate oxide layer and a third polysilicon layer are formed sequentially. Finally, the gate oxide layer and the third polysilicon layer are defined to form gate electrodes, that is, word lines for the memory.

REFERENCES:
patent: 5180680 (1993-01-01), Yang
patent: 5460987 (1995-10-01), Wen et al.
patent: 5504025 (1996-04-01), Fong-Chun et al.

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