Method of fabricating high density flash memory with self-aligne

Details Method of fabricating high density flash memory with self-aligne Method of fabricating high density flash memory with self-aligne

1999-05-06

2000-09-05

Smith, Matthew

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438257, 438265, 438594, H01L 21336, H01L 213205, H01L 214763

Patent

active

061142042

ABSTRACT:
A method of fabricating a flash memory cell. A spacer is formed on a sidewall of a controlling gate. A self-aligned source/drain region can thus be formed by the formation of the spacer. The tunneling oxide layer is then formed on the source/drain region instead of on the controlling gate. Thus, the tunneling oxide layer is formed with a self-aligned process.

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patent: 5970342 (1999-10-01), Wu
patent: 6001687 (1999-12-01), Chu et al.
patent: 6048768 (2000-04-01), Ding et al.

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