Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-04-06
2003-10-21
Chaudhurl, Olik (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S217000, C438S296000, C438S426000, C438S433000, C438S591000, C257S333000, C257S523000
Reexamination Certificate
active
06635537
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a method of fabricating a semiconductor integrated circuit. More particularly, this invention relates to a method of fabricating gate oxide layer.
2. Description of the Related Art
In the intensively developed semiconductor industry, how to reduce the device and increase the integration has become a leading trench in fabrication technique. When the dimension of the device is shrunk, the integration increases, the size of the device isolation has to be reduced consequently. The technique for fabricating the device isolation thus becomes more and more difficult. Local oxidation (LOCOS) is a common technique for fabricating a field oxide layer as the device isolation. However, due to the formation of a bird's beak, a leakage current is often caused, or even a white spot of image is formed. To apply this technique to form an isolation structure with a further reduce size thus becomes very difficult.
Thus, other techniques such as shallow trench isolation (STI) have been developed and widely applied. The shallow trench isolation has been intensively used in the sub-half micron integrated circuit.
The conventional method for fabricating a shallow trench isolation includes forming a pad oxide layer and a silicon nitride hard mask layer on a substrate. Using photolithography and etching process, a trench is formed in the substrate. Substrate around the trench is defined as an active region to provide formation of various active devices in the subsequent process.
A liner oxide layer is formed on a surface of the trench using thermal oxidation. The trench is then filled with a silicon oxide layer formed by chemical vapor deposition. The silicon oxide layer over the hard mask layer is then removed by chemical mechanical polishing. The silicon nitride hard mask layer and the pad oxide layer then removed to form the shallow trench isolation. Typically, hot phosphoric acid is used to remove the silicon nitride, and hydrogen fluoride is used to remove the pad oxide layer.
In the conventional process for fabricating the shallow trench isolation, an isotropic etching step is performed to remove the pad oxide layer and the hard mask layer. During the isotropic etching step, it is very easy to form a recess of the substrate at the top edge corner of the trench. As a result, a gate oxide layer formed subsequently has a thinner thickness around the shallow trench isolation. The thinner thickness may cause a parasitic device conductance, that is, the hump effect. In the subsequently process for forming a polysilicon layer as the gate, the top edge corner of the trench is covered by the gate to cause a large intensified field. A lower threshold voltage is resulted, and the sub-threshold leakage is increased. As the integrated circuit is fabricated with a smaller and smaller size, the local intensified field has a more and more serious effect on the sub-threshold leakage. Eventually, a gate oxide layer breakdown may be resulted.
SUMMARY OF THE INVENTION
The method provides a method of fabricating a gate oxide layer without reducing the active region. A hard mask layer is formed on a substrate. The hard mask layer and the substrate are patterned to form a trench in the substrate. A portion of the hard mask layer is removed to expose the substrate around the trench, that is, the substrate at a top edge corner of the trench is exposed. An insulation layer is formed to fill the trench over the exposed substrate and the remaining hard mask layer. The insulation layer over the surface level of the hard mask layer is removed. The remaining hard mask layer is removed to expose the substrate, while the substrate at the top edge corner of the trench is still covered with the insulation layer. An ion implantation step is performed on the exposed substrate to reduce the oxidation rate. The insulation layer over the surface level of the substrate is then removed to expose the substrate at the top edge corner of the trench. A gate is then formed on the substrate with a thicker thickness around the trench.
According to the invention, the ion implantation performed on the substrate provides a slower oxidation rate of the substrate. The substrate around the trench being covered with the insulation layer thus has an oxidation rate faster than the other position. As a result, the gate oxide layer has a thicker thickness around the trench, and a thinner thickness away from the trench. The problems such as parasitic device conductance, that is, the hump effect can be resolved.
In addition, the ion implantation is performed during the fabrication process of the shallow trench isolation with the insulation layer as a mask. That is, the ion implantation step is a self-aligned implantation step without forming additional masks. That is, the problems of the conventional method can be resolved by the invention without introducing any additional masks.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
REFERENCES:
patent: 6002160 (1999-12-01), He et al.
patent: 6323106 (2001-11-01), Huang et al.
patent: 6413826 (2002-07-01), Kim
Hsu Shih-Chien
Huang Chang-Chi
Huang Cheng-Tung
Lee Tong-Hsin
Lin Sheng-Hao
Berezny Neal
Chaudhurl Olik
J. C. Patents
United Microelectronics Corp.
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