Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-06-05
2002-09-24
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S307000, C438S549000
Reexamination Certificate
active
06455376
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90106862, filed Mar. 23, 2001.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of fabricating a memory. More particularly, the present invention relates to a method of fabricating a flash memory.
2. Description of Related Art
A flash memory is a non-volatile memory that can be programmable, erasable, and capable of saving data even after the power is cut off. It is a memory device that is widely adopted in manufacturing of personal computer (PC) and other electronic equipments.
Conventional method for fabricating a transistor memory cell usually involves, after formation of a stacked gate constituted of a tunnel oxide layer, a floating gate, a dielectric layer, and a control gate, performing a doping step on the substrate, with the stacked gate serving as a mask. With a long period of high temperature annealing, a source/drain region with a deeper junction is formed. Depending upon the specific channel length, an appropriate bias is supplied to the source/drain region. Next, hot electrons are produced in the channel by performing a channel hot electron injection, with some electrons passing through the tunnel oxide layer to the floating gate for programming the device. Besides, the source/drain region in the memory also serves as a diffusion path that connects to a bit line.
With a trend of high device integration, the device size is reduced according to the design rule, while the channel length of the floating gate is also reduced. Meanwhile, a depletion region produced from the source/drain region further reduces the channel length in such a way that the depletion region of the source may overlap with that of the drain. This has made problems such as short channel effect and punch-through leakage seem worse.
To resolve the problems associated with the increased device integration, the source/drain needs to be formed with a shallow drain junction. The shallow drain junction may have improved from the problems mentioned above, but with a shallow depth of the source/drain, the bit line that connects to the source/drain may show an increase of resistance, resulting a voltage drop at a junction where the bit line is connected to the source/drain. So, when the device is programmed by a channel hot electron injection, a large bias is supplied to the source/drain. This causes a serious loading effect since the voltage drop would have reduced the actual bias.
Summarizing the above, in the case where the size of the device is minimized, if the shallow drain junction is adopted to solve the short channel effect and the punch-through leakage, a loading effect of the source/drain would occur as a result. On the other hand, if the drain junction were deepened to resolve the loading effect, short channel effect and the punch through leakage would once again be a problem. Therefore, for the foregoing reasons stated above, the conventional fabrication methods for the flash memory cannot solve all the problems at once. Accordingly, it is difficult to practically reduce the size of the device during the fabrication.
SUMMARY OF THE INVENTION
The present invention provides a method of fabricating a flash memory to effectively improve from the short channel effect and punch through leakage.
The present invention also provides a method of fabricating the flash memory to reduce resistance at a junction where the bit line is connected to the source/drain, so as to improve from the loading effect.
The present invention further provides a method of fabricating the flash memory to reduces the size of the device while increasing the device integration.
To achieve these and other advantages and in accordance with the purpose of the invention, a method of fabricating the flash memory is provided, which method begins by providing a substrate. A stacked gate constituted of a tunnel oxide layer, a floating gate, a dielectric layer, and a control gate is formed on the substrate. A shallow junction doping is then performed on the substrate, with the stacked gate serving as a mask, so as to form a shallow junction doped region in the substrate adjacent to both sides of the stacked gate. A mask layer is formed on the substrate to cover a top surface and sidewalls of the stacked gate, while exposing portions of the shallow junction doped region. With the mask layer serving as a mask, a deep junction doping is further performed on the substrate to form a deep junction doped region in the substrate adjacent to both sides of the mask layer. After the mask layer is removed, a thermal process is performed to form a source/drain region having both the shallow junction doped region and deep junction doped region.
As embodied and broadly described herein, the source/drain regions having both shallow drain junction and a deep drain junction are formed according to the invention. Since the flash memory is formed as described above, formation of depletion regions of the source/drain regions can be effectively controlled, even if the channel length is reduced. Consequently, this improves from the short channel effect that is resulted from further reduction of the channel length caused by the depletion regions. Also, this improves from the punch through leakage produced outside the channel due to a close proximity of the depletion regions of the source/drain regions.
While a junction is made between the shallow drain junction and the bit line, a rise in resistance may be induced as a result of an insufficient junction depth. This leads to a voltage drop at the junction, resulting a loading effect. According to the present invention, the source/drain regions do not only provide the shallow drain junction, but also provide the deep drain junction. Therefore, the resistance of the source/drain regions is reduced, while the loading effect resulted from the insufficient junction depth of the source/drain regions is also effectively reduced.
Furthermore, since the source/drain regions of the flash memory formed according to the invention have both the shallow drain junction and the deep drain junction, problems such as short channel effect, punch-through leakage, loading effect and so on can all be effectively resolved at once. For the foregoing reason, it is appropriate to apply the method of the invention for designing the device with a minimized size. Accordingly, the memory device with a short channel can be manufactured, which in turn improves the integration of the memory device.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 6037223 (2000-03-01), Su et al.
patent: 6057192 (2000-05-01), Colabella
patent: 6329247 (2001-12-01), Ito
Fan Tso Hung
Lu Tao-Cheng
Tsai Wen-Jer
Chaudhari Chandra
J.C. Patents
Macronix International Co. Ltd.
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