Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-05-10
2005-05-10
Le, Dung A. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S258000, C438S259000, C257S314000, C257S315000, C257S316000
Reexamination Certificate
active
06890820
ABSTRACT:
A method of fabricating split gate type FLASH memory device comprises forming trench device isolation layers in a substrate to define a plurality of parallel first active regions. A gate insulation pattern, a conductive pattern and a hard mask pattern, which are sequentially stacked, are formed to have sidewalls aligned to sidewalls of the trench device isolation layer. Along each of the first active regions, the hard mask pattern is removed at regular intervals to expose a top of the conductive pattern. An oxide pattern is formed on the exposed top of the conductive pattern and the hard mask pattern is removed. Using the oxide pattern as an etch mask, the conductive pattern is etched to form floating gate patterns arranged over each of the first active regions at regular intervals. Tunnel oxide layers are formed on sidewalls of the floating gate patterns. A plurality of control gate electrodes are formed to cross over the first active regions. The control gate electrodes are disposed on the floating gate patterns.
REFERENCES:
patent: 6403494 (2002-06-01), Chu et al.
patent: 6451654 (2002-09-01), Lin et al.
patent: 20020055205 (2002-05-01), Lin et al.
patent: 20020072197 (2002-06-01), Kang et al.
Moon Chang-Rok
Yoon Jung-Lim
Yu Jae-Min
F. Chau & Associates LLC
Le Dung A.
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