Method of fabricating flash memory cell

Details Method of fabricating flash memory cell Method of fabricating flash memory cell

1998-11-09

2001-08-07

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S257000, C438S263000, C438S266000

Reexamination Certificate

active

06271091

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a flash memory cell and a method of fabricating the same. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for suppressing undesirable leakage current caused by an over-erasure.
2. Discussion of the Related Art
Generally, as a nonvolatile memory device, a flash memory cell having a laminated structure including a floating gate and a control gate maintains a high erasing rate by erasing memory array cells concurrently. The programming of the flash memory cell is carried out when hot electrons are injected into the floating gate from the channel by applying high voltage to the control gate. The ratio of the voltage applied to the floating gate to the voltage applied to the control gate is known as a coupling ratio. As the coupling ratio goes higher, the programming efficiency increases.
The erasure of the flash memory cell is achieved when high voltage is applied to a source region having a deep junction and electrons of the floating gate are injected into the source region or a substrate by the mechanism of Fowler-Nordheim tunneling. Generally, to enhance the erasing efficiency, the thickness of a gate oxide layer at the bottom part of the floating gate has to be reduced. However, the thin gate oxide layer may lower the voltage applied to the floating gate and thus reduce the coupling ratio. Therefore, it is required to maintain a higher coupling ratio to enhance the programming and erasure efficiencies without reducing the thickness of the gate oxide layer.
A conventional flash memory cell and a method of fabricating the same will now be explained with reference to FIG.
1
.
FIG. 1
is a cross-sectional view of the conventional flash memory cell. As shown in
FIG. 1
, the conventional flash memory cell includes a semiconductor substrate
11
, source and drain regions
24
and
23
in the substrate, a lightly-doped region
25
below the source region, a field oxide layer
13
at a field region of the substrate, a gate oxide layer
15
on the substrate
11
exclusive of a portion on the source and drain regions
24
and
23
and the field oxide layer
13
, a floating gate
17
on the gate oxide layer
15
, an interlevel insulating layer
19
on the floating gate
17
, and a control gate
21
on the interlevel insulating layer.
FIGS. 2A through 2D
are cross-sectional views illustrating the process steps for fabricating a conventional flash memory cell.
Referring to
FIG. 2A
, a field oxide layer
13
for defining an active region of a device is formed on the field region of a P-type substrate
11
using a LOCOS (Local Oxidation of Silicon) process. Then, thermal oxidation is performed on the exposed portion of the substrate
11
to form a gate oxide layer
15
. After a polysilicon doped with impurity is deposited on the field oxide layer
13
and the gate oxide layer
15
by CVD (Chemical Vapor Deposition), a floating gate
17
is finally formed by patterning a deposited polysilicon into a stripe shape in a direction parallel to the substrate
11
using photolithography.
Referring to
FIG. 2B
, an interlevel insulating layer
19
having an ONO (Oxide-Nitride-Oxide) structure is formed on the floating gate
17
.
Referring to
FIG. 2C
, after depositing a polysilicon layer on the interlevel insulating layer
19
, a control gate
21
is formed by patterning the deposited polysilicon into a stripe shape in a direction perpendicular to the substrate
11
using photolithography. In this process, portions of the interlevel insulating layer
19
, the floating gate
17
, and the gate oxide layer
15
exclusive of portions overlapping the control gate
21
are also removed.
Referring to
FIG. 2D
, source and drain regions
23
and
24
are formed by heavily implanting impurities of N-type, which is the opposite conductivity type of the substrate
11
, by using the control gate
21
as a mask. Then, a lightly-doped region
25
for forming a double diffusion drain structure is formed to partly overlap the floating gate
17
by lightly implanting N-type impurities to surround the drain region
24
. In this process, the lightly-doped region
25
may be formed prior to forming the source and drain regions
23
and
24
.
In the aforementioned flash memory device having the source region
23
connected to the ground, the device is programmed when the voltage Vg applied to the control gate
21
is higher than the voltage Vd applied to the drain region
24
. Hot electrons generated in the channel are then injected into the floating gate
17
. To erase programmed data in the flash memory cell, with the control gate
21
grounded, or with a negative voltage applied, the voltage Vs is applied to the source region and thus the electrons in the floating gate
17
are tunneled to the source region
23
or the substrate
11
.
However, the aforementioned conventional flash memory cell has some problems. For example, since a thin gate oxide layer causes a coupling ratio to be small, the programming efficiency is low. On the other hand, the thick gate oxide layer results in a low erasing efficiency. Furthermore, when the gate oxide layer is too thin, the memory cell may be damaged by hot electrons injected into the floating gate during programming. As a result, the reliability of the cell is low and an over-erasure may also occur during repeated erasures due to hot holes trapped by the gate oxide layer.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method of fabricating a flash memory cell that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method of fabricating a flash memory cell to increase programming efficiency and to overcome low erasing efficiency.
Another object of the present invention is to provide a method of fabricating a flash memory cell to prevent a gate oxide layer from being damaged by hot electrons injected into the floating gate during programming.
Another object of the present invention is to provide a method of fabricating a flash memory cell to prevent cell information from being damaged due to leakage current caused by an over-erasure even with repeated erasures.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a method of fabricating a flash memory cell includes the steps of forming a first gate oxide layer on a substrate of a first conductivity type, forming a floating gate being in a stripe shape in a first direction on the first gate oxide layer, forming an interlevel insulating layer, a control gate and a cap oxide layer being in a stripe shape in a second direction so as to perpendicularly superpose on the floating gate, and having first and second lateral surfaces, forming a sidewall insulating layer on the second lateral surfaces of the interlevel insulating layer, the control gate and the cap oxide layer, forming a lightly-doped region of a first conductivity type on the substrate on the second lateral surfaces of the control gate and the cap oxide layer, forming a second gate oxide layer on the first and second lateral surfaces of the floating gate and the control gate, forming a selection gate and an erase gate being in a sidewall form on the first and second lateral surfaces of the floating gate and the control gate, and forming a heavily-doped region of a second conductivity type on the substrate by using the cap oxide layer, the selection gate and the erase

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