Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-02-17
1999-11-30
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438286, H01L 21336
Patent
active
059941855
ABSTRACT:
A method of fabricating a flash memory. A heavily doped region with the opposite polarity of the drain region is formed between the channel region and the drain region. The heavily doped region is in a bar shape extending towards both the drain and the source regions along a side of the floating gate. Furthermore, the reading operation is performed in reverse by applying a zero voltage to the drain region, and a non-zero voltage to the source region.
REFERENCES:
patent: 3934159 (1976-01-01), Nomiya et al.
patent: 5065212 (1991-11-01), Ohata et al.
patent: 5138415 (1992-08-01), Yano
patent: 5178370 (1993-01-01), Clark et al.
patent: 5270230 (1993-12-01), Sakurai
patent: 5273917 (1993-12-01), Sakurai
patent: 5547880 (1996-08-01), Williams et al.
patent: 5591652 (1997-01-01), Matsushita
patent: 5804470 (1998-09-01), Wollesen
Hong Gary
Sheu Yau-Kae
Lindsay Jr. Walter L.
Niebling John F.
United Semiconductor Corp.
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