Method of fabricating flash memory

Details Method of fabricating flash memory Method of fabricating flash memory

2005-09-13

2005-09-13

Norton, Nadine G. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S696000, C438S699000, C438S705000, C438S719000, C438S723000, C438S724000

Reexamination Certificate

active

06943118

ABSTRACT:
In a method of fabricating a flash memory, a tunneling dielectric layer, a first conductive layer and a mask layer are sequentially formed on a substrate to form a gate structure. Buried source/drain regions are then formed in the substrate between the strips. The strips are further patterned into floating gate structures. An insulation layer is formed sideways adjacent to the gate structure. The insulation layer has a top surface lower than a top surface of the first conductive layer of the gate structure. The mask layer is removed, and an additional conductive layer is formed on the first conductive layer in a manner to extend over the adjacent insulation layer. The first and additional conductive layers form a floating gate. A gate dielectric layer is formed on the floating gate, and a control gate is formed on the gate dielectric layer.

REFERENCES:
patent: 6406961 (2002-06-01), Chen
patent: 6462372 (2002-10-01), Wu
patent: 6689658 (2004-02-01), Wu
patent: 6713834 (2004-03-01), Mori et al.
patent: 6791142 (2004-09-01), Tseng
patent: 6797565 (2004-09-01), Yang et al.
patent: 6818508 (2004-11-01), Shimizu et al.

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