Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-08-23
2001-06-05
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S286000
Reexamination Certificate
active
06242307
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a flash memory, and more particularly, to a method of fabricating a flash memory which can perform both erasing and programming by the Fowler-Nordheim tunneling effect.
2. Description of the Related Art
The gate of a conventional flash memory comprises a floating gate for charge storage and a control gate for data accessing. The floating gate is in a floating state without being connected to any electrical circuit and is located between the control gate and a substrate. The control gate is connected to a word line.
FIG. 1
schematically shows an equivalent circuit diagram according to the prior art. In
FIG. 1
, WL
1
and WL
2
are word lines, and BL
1
, BL
2
, BL
3
and BL
4
are bit lines. This is an arrangement that can achieve a higher integration density currently. The operation of the arrangement is to program from a drain region in a fashion of channel hot electron injection (CHEI) and to erase from a source region in a Fowler-Nordheim (FN) tunneling fashion. However, the CHEI needs a higher voltage to operate; it thus consumes more energy. Furthermore, with respect to programming speed, the CHEI operation is faster than the FN tunneling operation, but the CHEI operation may shorten the lifetime of a flash memory cell. Thus, the overall performance of a flash memory cell that both programs and erases by the FN tunneling operation is better than that of a flash memory cell that separately programs by a CHEI operation and erases by a FN tunneling operation.
In a conventional method for fabricating a flash memory as shown in
FIG. 1
, an oxide layer is formed on a substrate by thermal oxidation, and a bar-shaped first polysilicon layer is formed thereon. A dielectric layer and a second polysilicon layer are formed over the substrate. Subsequently, the second polysilicon layer, the dielectric layer and the bar-shaped polysilicon layer are patterned to form a bar-shaped control gate made of the second polysilicon layer perpendicular to the bar-shaped first polysilicon layer before being patterned which has been patterned to into multiple floating gates. Since the thickness of the tunneling oxide layer between the floating gate and the substrate is uniform, it is not suitable for programming and erasing by a FN tunneling operation. This is because adjacent memory cells affect each other in FN tunneling operations and the bit-by-bit definition cannot be performed. Therefore, if the FN tunneling operation is used to program and to erase for the device design, then such arrangement of cell memories having a high integration density cannot be adopted.
SUMMARY OF THE INVENTION
Therefore, the invention provides method of fabricating a flash memory, which has a high integration density for memory cells arrangement without the requirement of a device isolation structure between neighbor memory cell.
The invention provides a method of fabricating a flash memory by the following steps. A first conductive layer covering a first oxide layer is formed on a substrate. The first conductive layer and the first oxide layer are strip-like and extend along a first direction. A mask layer is formed to extend from a part of a top surface of the first conductive layer along a sidewall there of towards a part of the substrate exposed next to the first conductive layer. Therefore, a first side of the first oxide layer is covered by the mask layer, while a second side of the first oxide layer is exposed. Using the mask layer as a mask, the exposed first conductive layer and the exposed substrate are oxidized into a second oxide layer. As a consequence, the second side of the first oxide layer is expanded to form a bird's beak. The mask layer, the second oxide layer are removed. A doped region is formed in the substrate at each side of the first conductive layer. A dielectric layer and a second conductive layer are formed on the first conductive layer and the substrate. The dielectric layer, the second conductive layer, the first conductive layer and the first oxide layer are patterned to result in a strip-like controlling gate extending along a second direction perpendicular to the first direction and an island-like floating gate made of the patterned first conductive layer.
In accordance with the invention, since the thickness of the tunneling oxide layer close to the first bar-shaped doped region and that close to the second bar-shaped doped region are different, the tunneling oxide layer can bear with different voltages at two ends. Thus, the disturbance between adjacent memory cells during programming can thereby be avoided. Therefore, the flash memory provided by the invention can perform both programming and erasing by the FN tunneling operation without affecting the integration density, and the lifetime of the flash memory is further increased.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5620913 (1997-04-01), Lee
patent: 5633184 (1997-05-01), Tamura et al.
patent: 5633185 (1997-05-01), Yiu et al.
patent: 5885871 (1999-03-01), Chan et al.
patent: 6015736 (2000-01-01), Luning et al.
patent: 6025240 (2000-02-01), Chan et al.
patent: 6030869 (2000-02-01), Odake et al.
patent: 6066875 (2000-05-01), Chen
patent: 6090670 (2000-07-01), Sandhu et al.
patent: 6103576 (2000-08-01), Deustche et al.
Booth Richard
United Microelectronics Corp.
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