Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-03-19
2001-09-04
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S261000, C438S275000
Reexamination Certificate
active
06284597
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88101441, filed Jan. 30, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a fabrication method of a flash memory. More particularly, the present invention relates to a method of fabricating an NAND flash memory structure which provides a higher density memory device array.
2. Description of Related Art
A conventional flash memory structure is characterized by a gate structure having two layers. One layer is a floating gate, fabricated from polysilicon for storing charges, and is usually in a floating status without being connected to any other circuits. Another layer is a control gate for controlling the date access to the floating gate. For example, in a NAND flash memory, each floating gate of the flash memory is connected to a word line (W/L) and each source/drain region of the flash memory is connected in series to a bit line (B/L). Flash memory is a very popular Erasable Programmable Read-Only Memory (EPROM) which can provide faster programming and erasing. Conventionally, the read/write function of the flash memory is performed using Fowler-Nordheim tunneling between the floating gate and the doped region, the rate of which depends on the electron transmission speed between the floating gate and the doped region.
Manufacturing flash memory at a minimized size is necessary in semiconductor process; i.e. the distribution of flash memory needs to have a higher density in order to conform to the process requirements. But, in this case, the extent to minimize the size of the flash memory is limited, if the flash memory conforms to the design rule. Moreover, it is very difficult to fabricate a tunneling oxide layer between the floating gate and the substrate when the thickness of the tunneling oxide layer is required to be very thin. It is especially difficult to perform the alignment step. It is important to precisely conform to the Shallow Trench Isolation (STI) process, so that the unnecessary shorts and leakage resulting between the device and the substrate are prevented.
SUMMARY OF THE INVENTION
The invention provides a method for fabricating an improved flash memory structure. A tunneling oxide layer can be formed as a part of a more precise flash memory structure using a self-aligned method that conforms to STI process steps. It is appropriate to use in a high density memory device array.
In the invention, a method for fabricating a flash memory is provided with following steps. A substrate is provided with a pad oxide layer and a first insulating layer sequentially formed thereon. A photolithography and etching process is performed to expose a part of the pad oxide layer, wherein the substrate covered by the remaining first insulating layer is defined as an active region. With the first insulating layer serving as a mask, the pad oxide layer and the semiconductor substrate are etched to form a trench in the semiconductor. The trench is filled with a plug which serves as a shallow trench isolation. The surface of the plug is approximately levelled with the surface of the first insulating layer. The first insulating layer and the pad oxide layer are removed, so that the surface of the plug is projected above the substrate. A gate oxide layer is formed on the substrate. Spacer is formed on a sidewall of the plug projecting above the surface of the substrate. With the spacer serving as a mask, the gate oxide layer uncovered by the spacer is removed by etching while a part of the plug is also removed, so that the surface of the plug is lowered to some extent. Then, with the spacer and the plug serving as a mask, a self-aligned tunneling oxide layer is formed by thermal oxidation on the exposed substrate, and the spacer is removed thereafter. In addition, the floating gate is formed on the tunneling oxide layer, the gate oxide layer and a part of the plug. A dielectric layer and a control gate are formed in sequence on the floating oxide layer and the exposed plug, so that the flash memory structure is complete.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5516713 (1996-05-01), Hsue et al.
patent: 6060357 (2000-05-01), Lee
patent: 6180454 (2001-01-01), Chang et al.
Dang Phuc T.
Huang Jiawei
Nelms David
Patents J.C.
United Microelectronics Corp.
LandOfFree
Method of fabricating flash memory does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating flash memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating flash memory will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2455154