Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-12-30
2001-03-27
Nelms, David (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000, C438S269000
Reexamination Certificate
active
06207504
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87112424, filed July 29, 1998 the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of forming an erasable programmable read only memory (EEPROM).
2. Description of the Related Art
EPROM, an acronym for Erasable Programmable Read Only Memory, is the memory circuit that is most often used in computer and electronic products. One of its advantages is that neither the program, nor the data stored in the EPROM, are not lost under normal conditions. If there is a need to erase the stored program and data, it is simply exposed to an ultraviolet light source for a specified period of time. In this way, the EPROM can be reprogrammed again. However, the EPROM erase operation wipes out all the stored data residing within. Therefore, whenever a data update is required, every bit of data must be rewritten back to the EPROM, which is rather time-consuming. Technology for a flash EPROM was developed by Intel Corporation. The data does not need to be erased completely. Instead, the characteristic of the flash EPROM is to erase data block by block. Hence, the time for reprogramming a flash EPROM is reduced.
FIG. 1
is a top-view layout showing a conventional flash EPROM. In
FIG. 1
, the conventional flash EPROM includes an isolation structure
101
, a floating gate layer
103
, a control gate
105
, a common source region
106
, and a drain region
107
.
FIGS. 2A through 2C
are schematic, cross-sectional views of a portion of a semiconductor device showing the conventional steps of fabricating a flash EPROM. The (I) of each figure is a cross-sectional view of
FIG. 1
taken along line I—I. The (II) of each figure is a cross-sectional view of
FIG. 1
taken along line II—II. The (III) of each figure is a cross-sectional view of
FIG. 1
taken along line III—III.
In
FIG. 2A
, a P-type substrate
100
having a shallow trench (STI)
101
therein is provided. A tunnel oxide layer
102
and a floating gate layer
103
are formed in sequence over the substrate
100
, after which the tunnel oxide layer
102
and the floating gate layer
103
are patterned.
In
FIG. 2B
, a first isolation layer
104
and a control gate layer
105
are formed in sequence over the substrate
100
. The control gate layer
105
, the isolation layer
104
, the floating gate layer
103
, and the tunnel oxide layer
102
are patterned.
In
FIG. 2C
, an ion implantation step is performed to form a common source region
106
and drain regions
107
in the substrate
100
. Spacers
108
are formed over the sidewalls of the control gate layer
105
, the isolation layer
104
, the floating gate layer
103
, and the tunnel oxide layer
102
. Then, a self-aligned silicide step is performed to form silicide layers
109
on the control gate layer
105
, the common source region
106
, and the drain region
107
.
However, it is difficult to form the silicide layer
109
on an abrupt-step structure (show in
FIG. 2B
(II)) in the conventional process, in which the resistance of common source region
106
is increased. In
FIG. 2A
(II), the surface of the tunnel oxide layer
102
and the floating gate layer
103
is higher than the surface of substrate
100
. Therefore the surface over the substrate
100
is not flat. In
FIG. 2B
(II), an abrupt-step surface
113
is formed after patterning the control gate layer
105
, the isolation layer
104
, the floating gate layer
103
, and the tunnel oxide layer
102
. In
FIG. 2C
(II), it is difficult to perform a self-aligned silicide step on the surface of an abrupt-step structure
114
to form the silicide layer
109
thereon. Therefore, the resistance of the common source region
106
is increased.
SUMMARY OF THE INVENTION
Accordingly, there is a need to provide an improved method of fabricating a flash EPROM in order to form silicide layers on the whole surface of the common source regions in order to reduce the resistance of the common source regions.
The invention provides a method of fabricating a flash erasable programmable read only memory. A substrate having an isolation structure is provided. A tunnel oxide layer and a floating gate layer are formed in sequence over substrate and are patterned. A first-type ion implantation is performed to form a first doped region in the substrate. An oxidation step is performed to form a first oxide layer over the substrate. A nitride/oxide layer and a control gate layer are formed in sequence over the substrate. The control gate layer, the nitride/oxide layer, the first oxide layer, the floating gate layer are patterned until the substrate is exposed. An ion implantation step is performed with the isolation structure as a mask. A common source region and a drain region are formed in the substrate. Spacers are formed over the sidewalls of the control gate layer, the nitride/oxide layer, the first oxide layer, and the floating gate layer. A self-aligned silicide step is performed to form silicide layers over the control gate layer, the common source region, and the drain region.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 6040217 (2000-03-01), Lin et al.
Hsieh Alex
Lin Chih-Hung
Wu Chun-Ming
Dang Phuc T.
Huang Jiawei
J C Patents
Nelms David
United Semiconductor Corp.
LandOfFree
Method of fabricating flash erasable programmable read only... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating flash erasable programmable read only..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating flash erasable programmable read only... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2474668