Method of fabricating field effect transistor

Details Method of fabricating field effect transistor Method of fabricating field effect transistor

2000-10-12

2003-05-13

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S682000, C438S302000, C438S683000, C438S664000, C438S592000

Reexamination Certificate

active

06562685

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a field effect transistor (referred to hereinafter as a MOSFET), and in particular, to a method of fabricating a MOSFET having a source region as well as a drain region of a LDD (light doped drain) structure.
2. Description of the Related Art
In order to maintain pressure resistance without deteriorating device performance, it has been in practice to form the source region and the drain region into the LDD (light doped drain) structure. The LDD structure is a structure having a lightly doped region in comparison with the source region and the drain region, in a region directly beneath the gate electrode, within the source region and the drain region, respectively, and can be formed by implanting ions in two stages when forming the source region and the drain region.
For example, as shown in
FIG. 3
, by implanting a dopant such as arsenic ions As
+
or phosphorus ions P
+
, in low concentration, into the surface of a silicon substrate
30
on which there are formed device separation regions
32
, a gate oxide film
34
, and a gate electrode made up of a polysilicon layer
36
and a gate silicide layer
38
of tungsten silicide or so forth, deposited in layers on the gate oxide film
34
, in the direction vertical to the surface of the silicon substrate
30
, self-aligning ion implantation by the agency of the gate electrode is performed {refer to FIG.
3
(A)}.
That is, as a result of implantation of ions in low concentration, a source region
40
a
and a drain region
42
a
, which are in shallow junction state, are formed.
Thereafter, a SiO
2
film
44
is formed on the entire surface {refer to FIG.
3
(B)}, and by etch-backing, that is, by etching the entire surface of the SiO
2
film
44
and completing the etching when the top face of the gate electrode is exposed, a sidewall
46
made of SiO
2
is formed on both sides of the gate electrode {refer to FIG.
3
(C)}.
Subsequently, by implanting a dopant such as arsenic ions As
+
, phosphorus ions P
+
, or so forth, in high concentration, into the surface of the silicon substrate
30
in the direction vertical to the surface thereof, self-aligning ion implantation by the agency of the gate electrode provided with the sidewalls
46
is performed {refer to FIG.
3
(D)}.
At this point in time, as the regions directly beneath the gate electrode are blocked by the respective sidewalls
46
, and consequently, the ions can not be implanted thereinto, so that these regions remain in shallow junction state (that is, remaining as LDD regions) while the dopant in high concentration is implanted into other regions, which are rendered in deep junction state. Accordingly, a source region
40
and a drain region
42
, having the LDD region in the respective regions directly beneath the gate electrode, are formed.
However, with the conventional method as described above, there will arise a problem that since the SiO
2
film
44
is etched back when forming the sidewall
46
on both sides of the gate electrode, such etch-backing causes the gate oxide film
34
to be damaged, thereby deteriorating the performance of a MOSFET.
Further, there will arise another problem that since the sidewalls themselves contain a number of defects and the like, hot carriers are injected into the sidewalls when the MOSFET is in operation, thereby deteriorating the performance of the MOSFET.
To cope with the problems described above, the invention has been developed, and it is an object of the invention to provide a method of fabricating a MOSFET whereby a source region and a drain region, having a LDD region in respective regions of a silicon substrate, directly beneath the gate electrode, can be formed even without forming sidewalls.
SUMMARY OF THE INVENTION
In order to achieve the objects described above, a method of fabricating a field effect transistor, according to a first aspect of the invention, comprises a gate electrode forming step of forming a gate electrode layer by patterning a polysilicon layer formed on a gate oxide film provided on the surface of a substrate, and forming a gate electrode through selective growth of a silicide on the surface of the gate electrode layer, a first doping step of implanting ions into the upper surface of the substrate from a direction at a slant to the upper surface thereof such that a dopant in low concentration is introduced into regions directly beneath the edges of the gate electrode, and a second doping step of implanting ions into the upper surface of the substrate from the direction vertical to the upper surface of the substrate such that a dopant in high concentration is introduced.
That is, with the gate electrode forming step according to the first aspect of the invention, selective growth of the silicide is caused to take place on the surface of the gate electrode layer, and consequently, a silicide layer is formed on the side faces of the gate electrode as well. In the course of the first doping step, since ions are implanted into the upper surface of the substrate from a direction at a slant to the upper surface thereof such that a dopant in low concentration is introduced into regions directly beneath the edges of the gate electrode, a source region and a drain region, in desirably shallow junction state, can be formed in the regions directly beneath the edges of the gate electrode as well.
In the course of the second doping step, since ions are implanted into the upper surface of the substrate from the direction vertical to the upper surface thereof, the silicide layer formed on the side faces of the gate electrode covers up the regions directly beneath the edges of the gate electrode, thereby preventing ions from being implanted therein with ease. Accordingly, the regions directly beneath the edges of the gate electrode wherein ions are prevented from being implanted will remain in shallow junction state (that is, remaining as LDD regions) while other regions wherein a dopant in high concentration is implanted will be in deep junction state. Thus, the source region and the drain region, having the LDD region, respectively, can be formed in the regions directly beneath the edges of the gate electrode.
With these features, the dopant used for the implantation of ions may include, for example, at least either of arsenic and phosphorus in the case of an N-channel MOSFET, and may include, for example, at least either of boron and boron fluoride in the case of a P-channel MOSFET.


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