Method of fabricating embedded DRAM

Details Method of fabricating embedded DRAM Method of fabricating embedded DRAM

1998-12-15

2001-06-05

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S239000, C438S253000

Reexamination Certificate

active

06242296

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method of fabricating an integrated circuit, and more particularly to a method of fabricating an embedded dynamic random access memory (embedded DRAM).
2. Description of the Related Art
In the general fabricating process of embedded DRAM, in order to enhance the conductivity and reduce the contact resistance of source/drain region of the transistor in the logic circuitry region, a salicide is formed on the source/drain region of the substrate by self-aligned silicide process. The process to fabricate the bit line and the capacitor are then performed in the memory region when the salicide and the doped region are already formed in the logic circuitry region. The major material of the capacitor dielectric layer currently is ONO or Ta
2
O
5
and it is necessary to perform a high temperature thermal process to form the capacitor dielectric layer. However, the high temperature thermal process causes diffusion of ions in the doped region of the logic circuitry region. When the size of the device is gradually reduced, the short channel effect and punch through are easily occurred in the substrate due to the diffusion of the doped region and as a result, the reliability of the devices is degraded.
In addition, the high temperature process causes the agglomeration of the salicide and its volume is therefore reduced when the thermal process is performed after the formation of the salicide. The resistance of the salicide is hence increased to lower the performance of the salicide since agglomeration.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a method of fabricating an embedded DRAM. The thermal process for the formation of the capacitor is prior to the formation of the doped region in the logic circuitry region to prevent diffusion occurred seriously in the doped region, and the reliability of device can be thus enhanced.
It is therefore an object of the invention to provide a method of fabricating an embedded DRAM. The thermal process for the formation of the capacitor is prior to the formation of the salicide to lower the probability that the agglomeration of the salicide is occurred, and the conductivity of the salicide can be improved.
To achieve these objects and advantages, and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed towards a method of fabricating an embedded DRAM. A word line and a gate are formed in a memory region and a logic circuitry region on the substrate. An etching stop layer is formed over the substrate and an array memory of the memory region is fabricated within a dielectric layer covered the etching stop layer. Using the etching stop layer as a stop point, the dielectric layer in the logic circuitry region is removed. The etching stop layer in the logic circuitry region is then removed to expose the gate and the substrate. A high-energy threshold adjust implantation is performed through the gate to form a retrograde channel profile. A source/drain region is formed in the substrate beside the gate in the logic circuitry region and a salicide is formed on the source/drain region.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 5248627 (1993-09-01), Williams
patent: 5296399 (1994-03-01), Park
patent: 5930618 (1999-07-01), Sun et al.

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