Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-04-14
2004-08-10
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S594000, C438S714000, C438S723000, C438S756000, C438S924000, C438S981000
Reexamination Certificate
active
06773991
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a nonvolatile semiconductor memory that includes a floating gate electrode and a control gate electrode and performs tunnel injection and erasure using a tunnel window area as a local thin oxide area.
2. Description of Related Art
Conventionally, there has been a rewriting data device that carries electrons through a tunneling phenomenon between a floating electrode and a diffusion layer formed on a substrate through a thin gate oxide film (tunnel oxide film) called a tunnel window area that has an opening on the diffusion layer in an electrically programmable/erasable read only memory (EEPROM) including a floating gate electrode and a control gate electrode.
Here, for a method of fabricating the above-mentioned EEPROM, a method of forming the tunnel window area in an EEPROM cell portion is chiefly explained with respect to
FIGS. 1A-1H
. An oxide film
2
, the thickness of which is 200 Angstroms, for example, is formed on a p-type silicon (Si) substrate
1
, and then a window opening
4
is formed by wet-etching a part of the oxide film
2
using a solvent such as hydrofluoric acid using a resist
3
as a mask (
FIGS. 1A
to
1
C).
Subsequently, the resist
3
is removed by an ashing process, the oxide film
2
is oxidized again, and a gate oxide film
6
, which has a locally thinned tunnel oxide film
5
that has a thickness of about 100 Angstroms, is locally formed in the window opening
4
(FIGS. ID and IE). Then, after polysilicon
7
as the floating electrode is deposited, polysilicon
7
is etched using a resist
8
as a mask, and a floating gate electrode
9
is formed so as to cover the window opening
4
(
FIGS. 1F
to
1
H).
In accordance with the disclosed conventional method, in view of any etching damage, etc., performing a wet-etching process forms a tunnel window opening. However, in the wet-etching process, there have been problems including seeping of, or side etching by the etching solvent, and furthermore there have been problems where it has been difficult to form a very small tunnel window opening.
SUMMARY OF THE INVENTION
It is a primary object of this invention to provide a method of avoiding seeping or side etching of etching solvent and to form a very small tunnel window opening.
Here, all of the necessary characteristics which the-present invention requires are not disclosed in the summary of the invention, but sub-combinations of these characteristics can also be the present invention.
The present invention is a method for fabricating an MOS transistor which includes a floating gate electrode and a film portion for a tunnel injection into the floating electrode, including a forming process for forming a first oxide film and a further first polysilicon layer on a semiconductor substrate; an introducing process for selectively introducing BF2 ions to a polysilicon portion outside a region of the film portion; an etching process for selectively etching polysilicon on the portion of the film where BF2 ions are not implanted; an oxidation process for oxidizing all of the polysilicon remaining after performing the etching process on an oxide film; and a polysilicon forming process for forming polysilicon as a floating gate electrode in a portion including a region of the film. The etching process is a wet etching process using a mixed solvent of hydrofluoric acid, nitric acid, and acetic acid.
The present invention is a method for fabricating an MOS transistor which includes a floating gate electrode and a film portion for a tunnel injection into the floating electrode including a forming process for forming a first oxide film on a semiconductor substrate; an introducing process for selectively introducing heavily concentrated impurities into a region of the film of the oxide film; an etching process for selectively etching the oxide film of the portion of the film where the heavily concentrated impurities are introduced; a forming process for performing an oxidizing process and forming an oxide film on the film; and a polysilicon forming process for forming polysilicon as a floating gate electrode in a portion including a region of the film. The heavily concentrated impurities are arsenic and hydrofluoric acid. The etching process is a wet-etching process using a hydrofluoric acid solvent. The etching process is a dry-etching process using a mixed gas of CF4 and O2.
The present invention selectively introduces heavily concentrated impurities into a portion outside a polysilicon region of a region of a tunnel window area, a polysilicon portion where impurities are not introduced is selectively etched, and then a tunnel oxide film is formed in the tunnel window area by oxidizing residual polysilicon.
Furthermore, the present invention selectively introduces heavily concentrated impurities into the region of the tunnel window area after the oxide film is formed, and it becomes possible to form the tunnel oxide film in the tunnel window area by selectively etching the oxide film where impurities are introduced and then wholly oxidizing. As a result, according to the present invention, it is possible to control the diameter of the tunnel window area in an easy manner, and thus it is possible to form a very small EEPROM memory cell.
REFERENCES:
patent: 4450041 (1984-05-01), Aklufi
patent: 4931847 (1990-06-01), Corda
patent: 5316981 (1994-05-01), Gardner et al.
patent: 5379253 (1995-01-01), Bergemont
patent: 5411904 (1995-05-01), Yamauchi et al.
patent: 6027972 (2000-02-01), Kerber
patent: 6573141 (2003-06-01), Kickel et al.
Oki Electric Industry Co, Ltd.
Rabin & Berdo P.C.
Thomas Toniae M.
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