Method of fabricating EEPROM

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C438S258000, C438S263000, C438S264000, C257S314000, C257S315000, C257SE27059, C257SE27060

Reexamination Certificate

active

08030159

ABSTRACT:
There is provided a method of fabricating an EEPROM for forming a memory cell transistor and a selection transistor, the method includes: forming a first source region and a first drain region of the memory cell transistor; forming a first gate oxide film; forming a resist having at least one through hole on the first gate oxide film; adding conductivity type impurities through the through hole; partially removing the first gate oxide film and forming a tunnel oxide film in a region corresponding to the through hole; forming a floating gate electrode and a second gate oxide film formed on the floating gate electrode; forming a control gate electrode and a selection transistor gate electrode on the second gate oxide film and at a region in which the selection transistor is formed; and forming a second source region and a second drain region of the selection transistor.

REFERENCES:
patent: 6506646 (2003-01-01), Miyagi
patent: 6680225 (2004-01-01), Miyagi
patent: 2001-210730 (2001-08-01), None

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