Method of fabricating dynamic random access memory

Details Method of fabricating dynamic random access memory Method of fabricating dynamic random access memory

1996-04-03

1998-12-22

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438254, 438396, 438397, 438585, H01L 218242

Patent

active

058518720

ABSTRACT:
A method of fabricating a DRAM which includes a capacitor and a metal oxide semiconductor field effect transistor. A field oxide layer is formed on a silicon substrate. A gate oxide layer is formed on the silicon substrate. A first polysilicon layer is deposited on the gate oxide layer. An insulator is deposited on the first polysilicon layer. A first silicon nitride layer is deposited on the insulator. The first silicon nitride layer, the insulator, the first polysilicon layer and the gate oxide layer are processed to form a gate electrode. First spacers are formed between the insulator and the substrate on sidewall on opposite sides of the gate electrode. Source-drain regions are formed on the substrate on the opposite sides of the gate electrode. A contact window is formed on the drain electrode. Second spacers are formed on surfaces of the first spacers which are adjacent to the contact window. A second silicon nitride layer is deposited on a surface of the first silicon nitride layer and a surface of the first spacers which are remote from the contact window. A second polysilicon layer is deposited on the contact window as a charge storage electrode of the capacitor. The first silicon nitride layer and the second silicon nitride layer are removed. A dielectric layer is deposited on the surface of the second polysilicon layer. A third polysilicon layer is deposited on the dielectric layer as the cell plate of the capacitor.

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