Method of fabricating dual gate electrode of CMOS...

Details Method of fabricating dual gate electrode of CMOS... Method of fabricating dual gate electrode of CMOS...

2006-08-17

2008-07-22

Le, Thao P. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE27108

Reexamination Certificate

active

07402478

ABSTRACT:
In an embodiment, a method of fabricating a dual gate electrode includes forming an initial semiconductor layer doped with impurities of a first conductivity type on a semiconductor substrate having a first region and a second region. The initial semiconductor layer of the second region is partially etched to form a recessed semiconductor layer that is thinner than the initial semiconductor layer. Impurities of a second conductivity type different from the first conductivity type are implanted into the recessed semiconductor layer to define a first semiconductor layer in the first region and a second semiconductor layer in the second region, respectively. Then, the first and second semiconductor layers are annealed, and the annealed first semiconductor layer is planarized. The resulting structure may be etched to form gate electrodes that are capable of having high concentrations of impurities.

REFERENCES:
patent: 6624019 (2003-09-01), Kim
patent: 6939757 (2005-09-01), Kim
patent: 7307273 (2007-12-01), Currie
patent: 7332388 (2008-02-01), Trivedi et al.
patent: 2007/0178633 (2007-08-01), Adetutu et al.
patent: 1998-0058454 (1998-10-01), None
patent: 2001-0045183 (2001-06-01), None
patent: 2002-0002155 (2002-01-01), None
English language abstract of Korean Publication No. 1998-0058454.
English language abstract of Korean Publication No. 2001-0045183
English language abstract of Korean Publication No. 2002-0002155.

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