Method of fabricating DRAM cell with capacitor having multiple c

Details Method of fabricating DRAM cell with capacitor having multiple c Method of fabricating DRAM cell with capacitor having multiple c

1997-12-29

1999-03-02

Chang, Joni

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438397, H01L 218242

Patent

active

058770534

ABSTRACT:
This invention discloses a novel design for increasing the surface area of a stacked capacitor used in DRAM devices. The upper and lower plates of the capacitor comprises of several concave structures. The concave structures are first produces on an LS-SOG layer using focused ion beam lithography, which is then mapped to the lower plate of the capacitor. A dielectric layer is deposited, after which an upper plate is formed. The concave structures increases the plate area, thereby increasing charge storage capacity.

REFERENCES:
patent: 5104821 (1992-04-01), Choi et al.
patent: 5459344 (1995-10-01), Wakamiya et al.
patent: 5565029 (1996-10-01), Takasu
patent: 5691115 (1997-11-01), Okamoto et al.

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