Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-06-28
2004-03-16
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S954000
Reexamination Certificate
active
06706598
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a method of fabricating nitride read-only memory (NROM) cells, and more particularly to the method of fabricating discrete NROM cell by self-aligned process.
2. Description of the Related Art
The memory devices for non-volatile storage of information, such as read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), and other advanced memory devices, are currently used in the worldwide industries. The other advanced memory devices that involve more complex processing and testing procedures include electrically erasable programmable read only memory (EEPROM), flash EEPROM, and nitride read-only memory (NROM). These advanced memory devices can accomplish the tasks that ROM can't do. For example, using EEPROM devices in circuitry permits in-circuit erasing and reprogramming of the device.
The main characteristic of NROM is dual bit cells having multiple threshold voltage levels, where every two threshold voltage levels together store a different bit. Others store one bit on either side of the cell. The conventional structures and fabricating methods of NROM cell are described in a lot of articles and references. For example, a dual bit cell of NROM cell is disclosed in U.S. Pat. No. 6,215,148, entitled “NROM cell with improved programming, erasing and cycling”. The process of NROM cell is disclosed in U.S. Pat. No. 6,201,282, entitled “Two bit ROM cell and process for producing same”. The disclosure of the above-identified patent is incorporated herein by reference.
FIG. 1
is a cross-sectional view of conventional NROM cells. The substrate
10
is implanted with a source
12
and a drain
14
. The top of the substrate
10
includes a sandwiched structure having a nitride layer
17
between a top oxide layer
16
and a bottom oxide layer (tunneling oxide layer)
18
, the so-called “ONO” structure. A number of BD (buried diffusion) oxide portions
20
are formed to isolate the adjacent ONO structure and form the channels
22
. The structure of an NROM cell, which contains dual bits in one cell, is also depicted in FIG.
1
. The larger region (encircled with the dashed line) denotes an NROM cell
30
, and the two smaller regions encircled with the dashed line denote the first bit
32
and the second bit
34
.
In the NROM cell, the nitride layer
17
provides the charge retention mechanism for programming the memory cell. Under normal condition, the electrons are introduced into the nitride layer
17
during a reading of the cell, while the holes are introduced into the nitride layer
17
to replace the electrons during an un-reading of the cell. Simply stated, the electrons should be able to move between the nitride layer
17
and the implant. However, nitride tends to trap electrons that are introduced in the nitride layer
17
due to its structure. If the electrons are trapped and un-removable, the cell programming function fades out or the whole cell is even ruined.
Additionally, according to the hot electron injection phenomenon, some hot electrons will penetrate through the bottom oxide layer
18
, especially when it is thin, and then collected in the nitride layer
17
. Concentrated charge caused by the hot electrons significantly raises the threshold of the portion of the channel
22
under charge to be higher than the threshold of the remaining portion of the channel
22
. When the cell is programmed, the concentrated charge is presented and the raised threshold does not permit the cell to reach the conductive state. In a normal state, which the concentrated charge is not presented, the reading voltage over the channel can overcome the threshold of the channel
22
and consequently the channel
22
is conductive.
Moreover, the conventional NROM cell is fabricated by using several steps of photolithography. The implant and the bits are not easily formed at the right position could be shifted, so that the efficiency of the NROM cell is decreased.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a method of fabricating discrete NROM cell by self-aligned process, so that the problem of electrons trapped in the nitride layer of the NROM cell can be solved, and also the mutual positions of the implant and ONO structure can be exactly controlled.
The invention achieves the above-identified objects by providing a method of fabricating a discrete NROM cell by a self aligned process, comprising the steps of providing a substrate with already formed an ONO layer, wherein the ONO layer includes a top oxide layer, a nitride layer and a bottom oxide layer; etching the top oxide layer to form a discrete top oxide layer; forming a plurality of disposable spacers at the sidewalls of the discrete top oxide layer; implanting buried bit line and pocket implant by the self-aligned process; removing the discrete top oxide layer and etching the nitride layer according to the disposable spacers; removing the disposable spacers to form a plurality of discrete nitrides; etching the bottom oxide layer according to the discrete nitride layer to form a plurality of discrete pillars, so that a channel is formed between two discrete pillars; forming a plurality of channel oxides in the channels; and forming an oxide layer over the discrete channel oxides and the discrete nitrides.
REFERENCES:
patent: 6436778 (2002-08-01), Fang et al.
Cuneo Kamand
Macronix International Co. Ltd.
Rabin & Berdo P.C.
Sarkar Asok Kumar
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