Method of fabricating dielectric layer

Details Method of fabricating dielectric layer Method of fabricating dielectric layer

1999-05-06

2001-06-12

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S261000, C438S287000, C438S775000, C438S954000

Reexamination Certificate

active

06245617

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of fabricating a dielectric layer comprising a multiple nitride layer structure.
2. Description of the Related Art
Dielectric layers are widely used in integration circuits. The quality and the structure of the dielectric layers are important factors for a integration circuit fabrication. For example, in a DRAM fabrication process, a cell comprises a transistor and a capacitor. The capacitor comprises a dielectric layer between a top electrode and a bottom electrode. The thickness and the structure of the dielectric layer used in the capacitor affect the capacity and the quality of the capacitor. The dielectric layer is used to store electrons. Electron storage capacity is related to the dielectric constant and the thickness of the dielectric layer. In addition, the time for preserving the storage electrons is affected by the quality of the dielectric layer. Thus, it is desirable to fabricate an improved dielectric layer.
In a current fabrication process of an integration circuit, the frequently used materials of the dielectric layer are oxide and nitride. Because the nitride has low dielectric constant and the oxide has a good adhesion ability, an oxide
itride/oxide structure are commonly used in the dielectric layer of the capacitor.
FIG. 1
is a schematic, cross-sectional view of a conventional dielectric layer comprising an oxide
itride/oxide structure.
In
FIG. 1
, a RCA cleaning step is performed on a polysilicon layer
100
. A HF surface treatment is performed on the polysilicon layer
100
. A native oxide layer is formed on the polysilicon layer
100
. The native oxide layer serves as a first oxide layer
102
of the conventional dielectric layer. A nitride layer
104
is formed on the first oxide layer
102
by deposition with a mixed gas source. The mixed gas source is mixed from SiH
2
Cl
2
and NH
3
having a ratio of 1:10. A portion of the nitride layer
104
on the surface is oxidized. A second oxidation layer
106
thus is formed on the nitride layer
104
. A dielectric layer comprising an oxide
itride/oxide structure is formed.
In the conventional dielectric layer, only one nitride layer is used. Once defects are formed in the nitride layer, or the nitride layer is damaged in a subsequent step, current leakage is likely to occur. The current leakage causes the electrons stored in the capacitor to be lost. This, in turn, reduces the electron-preserving time for the capacitor. Therefore, the electron-refreshing step must be performed more frequently. However, frequently performing the electron-refreshing step decreases the operation speed. Thus, problems are still encountered.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating a dielectric layer. A RCA cleaning step is performed on a polysilicon layer to remove impurities on the polysilicon layer. A HF surface treatment step is performed on the polysilicon layer. While performing the HF surface treatment step, a native oxide layer is formed on the polysilicon layer. The native oxide layer serves as a first oxide layer. A first mixed gas source is mixed from SiH
2
Cl
2
and NH
3
having a ratio of 1:3. Chemical vapor deposition is performed with the first mixed gas source to form a silicon-rich nitride layer on the first oxide layer. An NH
3
surface treatment is performed on the silicon-rich nitride layer to remove the native oxide layer on the silicon-rich nitride layer and improve the adhesion ability of the silicon-rich nitride layer. A second mixed gas source is mixed from SiH
2
Cl
2
:NH
3
having a preferred ratio of about 1:10 to 1:20. Chemical vapor deposition is performed to form a silicon-poor nitride layer on the silicon-rich nitride layer. After the silicon-poor nitride layer is formed, an NH
3
surface treatment is performed on the silicon-poor nitride layer. An oxidation step is performed on the surface of the silicon-poor nitride layer. A portion of the silicon-poor nitride layer is oxidized into a second oxide layer. A dielectric layer having a multiple nitride layer structure is formed.
The present invention forms the silicon-rich nitride layer and the silicon-poor nitride layer with the first and the second mixed gas sources, respectively. The first and the second mixed gas sources are mixed from SiH
2
Cl
2
and NH
3
with different ratios. The silicon-rich nitride layer enhances the adhesion ability for the first oxide layer. The silicon-rich nitride layer and the silicon-poor nitride layer together form a multiple nitride layer structure. The multiple nitride layer structure decreases the paths for current to flow into the oxide layer or the polysilicon layer during current leakage. Thus, the multiple nitride layer structure prevents the occurrence of current leakage.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5578848 (1996-11-01), Kwong et al.
patent: 5981403 (1999-11-01), Ma et al.
patent: 6051511 (2000-04-01), Thakur et al.
Wolf, Silicon Processing for the VLSI Era, vol. 1; Process Technology, Wolf et al.pp. 516-517, 1986, No Month.

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