Method of fabricating deep trench capacitor

Details Method of fabricating deep trench capacitor Method of fabricating deep trench capacitor

2001-01-04

2002-07-23

Ho, Hoai V. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S386000

Reexamination Certificate

active

06423594

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a method of fabricating a capacitor. More particularly, this invention relates to a method of fabricating a deep trench capacitor that can be formed in a dynamic random access memory cell.
2. Description of the Related Art
As the semiconductor fabrication process has approached to a stage of deep sub-micron, a great demand in reducing the dimension of devices is evoked. However, as the software has been developed with more and more functions that require a large capacity for accessing and storing data, the capacitor in a memory has to be formed with large enough capacitance when shrinking the device dimension. Methods to increase the capacitance of a capacitor includes reducing the thickness of the dielectric layer, using a dielectric layer with a higher dielectric constant and increasing the surface area of the capacitor electrode. Currently, the former two methods still have difficulty that may seriously affect the reliability and yield of products.
Therefore, the method of increasing surface area of capacitor electrode becomes a mainstream in increasing capacitance. As mentioned above, the reduction in dimension has been greatly demanded for fabricating an advanced device, the planar area available for fabricating the capacitor is thus very restricted. To increase the surface area of capacitor electrode without occupying a large planar area, the stack capacitor and deep trench capacitor have been widely employed in manufacturing.
For the stack capacitor, structure of hemispherical grain (HSG) has also been developed for further increasing the surface area of the electrode. The stack capacitor includes crown structure, fin structure, cylinder structure and spread structure. Among all the structures, a serious problem in planarization disadvantage to size reduction for devices has occurred to affect the subsequent fabrication process such as photolithography.
In a conventional trench capacitor, establishing an electrical connection between the capacitor and the drain region of the transistor is a crucial topic. Two methods including forming conductive surface strap (SS) and conductive buried strap (BS) have been used in the prior art. The method of forming conductive surface strap can establish a shallow direct contact between the capacitor and the drain region of the transistor, however, an additional photomask is required. Therefore, currently, the method for forming conductive buried strap is preferred.
In the conventional method for forming the buried strap, the electrical connection between the capacitor and the drain region is obtained by a direct contact between a doped polysilicon layer used as a node electrode of the capacitor and the drain region. After performing thermal treatments subsequently, the dopant contained within the doped polysilicon layer will easily diffuse into the drain region to form a deep junction. The electrical performance of the device is thus degraded seriously.
In addition, when misalignment occurs the electrical performance of device may also be degraded. Therefore, the design rule has to be relaxed, otherwise the process window will be narrowed.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating a trench capacitor using a shallow trench surface strap. A substrate is provided. A patterned mask layer is used to expose a portion of the substrate where a deep trench is to be formed. The exposed portion of the substrate is etched to form a deep trench. A conductive diffusion region is formed in the substrate surrounding the lower portion of the deep trench. A dielectric layer along an inner surface of the deep trench. The deep trench is filled with a first doped polysilicon layer. The first doped polysilicon layer and the dielectric layer are etched back to a first depth, so that a first recess is formed on the first doped polysilicon layer to expose the upper portion of the inner sidewall of the deep trench. A collar dielectric layer is formed on the exposed inner sidewall of the trench. The first recess is filled with a second doped polysilicon layer. The second doped polysilicon layer is etched back to a second depth, so that a second recess is formed on the second doped polysilicon layer to expose a part of the upper portion of the inner sidewall of the trench. The collar dielectric layer is etched by a wet etch process that its lower surface level is lower than the surface level of the second doped polysilicon layer, so that a gap is formed on the collar dielectric layer between the exposed inner sidewall of the deep trench and the second doped polysilicon layer. The gap is then filled with an undoped thin polysilicon layer and is CMP back to form a spacer, and etched back until the spacer top is at the same height as the silicon surface.
Using the method provided by the invention, a deep trench capacitor is formed without causing the problems in planarization. In addition, the electrical connection between the deep trench capacitor and the drain region of a transistor is established by the formation of an undoped polysilicon adjacent to the drain region. Therefore, the drawbacks of dopant diffusion caused by thermal treatment are eliminated. The thermal budget can thus be increased without causing the degradation of electrical performance. Furthermore, the process window can be widened.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 6368912 (2002-04-01), Chang et al.

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