Method of fabricating deep sub-micron CMOS source/drain with...

Details Method of fabricating deep sub-micron CMOS source/drain with... Method of fabricating deep sub-micron CMOS source/drain with...

2001-10-25

2004-08-24

Ghyka, Alexander (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S220000, C438S299000

Reexamination Certificate

active

06780700

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to metal-oxide-semiconductor (MOS) and complimentary metal-oxide-semiconductor (CMOS) integrated circuit (IC) fabrication processes, and specifically to a new process requiring fewer steps than conventional sub-micron MOS and CMOS fabrication processes.
BACKGROUND OF THE INVENTION
Known state-of-the-art processes for fabricating source/drain regions of active devices in integrated circuits including MOS and CMOS transistors require implantation of low dose ions, which is known as LDD implantation, followed by the formation of a gate sidewall insulator and n+ and p+ ion implantation. After n+ and p+ ion implantation, a salicide process generally is required to reduce any parasitic resistance in the source/drain region of the device. This requires, using conventional fabrication techniques, four separate masks operations: two masks are required for LDD ion implantation, a third mask is required for n+ ion implantation and a fourth mask is required for p+ ion implantation. An example of a salicide process is the deposition of a refractory metal, followed by a rapid thermal annealing (RTA) process to form a mono-silicide. After RTA, the un-reacted metal is etched away, followed by another RTA step to form a low resistance di-silicide.
It would be advantageous to have a method of fabricating MOS devices and CMOS devices in which the number of mask levels and ion implantation steps are reduced.
It would also be advantageous to have such a method in which a silicide layer is provided using only a single selective CVD silicide deposition.
SUMMARY OF THE INVENTION
The invention provides a method of forming a MOS device on a silicon substrate. Steps in one illustrative embodiment of the invention comprise preparing a substrate to contain a conductive region of a first conductivity type having a first device active area; forming a gate electrode structure on the first device active area, the gate electrode structure including a gate electrode and insulating sidewalls; implanting ions of an opposite conductivity type from that of said first device active area into the exposed portions of said conductive region to form source and drain regions on opposite sides of said gate structure; and depositing by selective CVD a silicide layer over said source and drain regions.
The preferred method of the invention further includes, in the implanting step, implanting ions using plasma immersion ion implantation at an energy in a range of about 0.5 keV to 2 keV, a dose in a range of about 1.0×10
14
cm
−2
to 1.0×10
15
cm
−2
, to yield a surface ion concentration in the source and drain regions in a range of about 1.0×10
19
cm
−3
to 1.0×10
22
cm
−3
.
An alternative perferred embodiment of the invention provides for carrying out the implanting step, using low energy ion implantation, before the formation of the gate sidewalls. When low energy ion implantation is used, ion implantation is carried out at an energy in a range of about 0.5 keV to 10 keV, a dose in a range of about 1.0×10
14
cm
−2
to 1.0×10
15
cm
−2
, to yield a surface ion concentration in the source and drain regions in a range of about 1.0×10
19
cm
−3
to 1.0×10
22
cm
−3
.
In another alternative embodiment of the invention, a method of forming a CMOS device on a silicon substrate is provided. In this embodiment the substrate is prepared to contain a conductive region of a first type having a first device active area therein; and to contain a conductive region of a second type having a second device active area therein. Steps further include forming a gate electrode on the first and second active areas; depositing and forming a gate electrode sidewall insulator layer on each gate electrode; masking the conductive region of the first type; implanting ions of a first type into the exposed portions of the conductive region of the second type to form a source region and a drain; stripping the mask; masking the conductive region of the second type; implanting ions of a second type into the exposed portions of the conductive region of the first type to form a source region and a drain region; stripping the mask; and depositing, preferably by selective CVD, a silicide layer over the source/drain regions of the first and second device active areas.
Additional steps in the alternative embodiment include implanting ions to form the source/drain regions using plasma immersion ion implantation as described above.
In a further embodiment of the present invention, CMOS devices are formed by the above-described steps except that the ion implantation is carried out before the gate sidewalls are formed using low energy ion implantation, and the gate sidewalls are formed after the ion implantation steps.


REFERENCES:
patent: 4703551 (1987-11-01), Szluk et al.
patent: 5757045 (1998-05-01), Tsai et al.
patent: 6069044 (2000-05-01), Wu
Article entitled, “Selectivity to Silicon Nitride in Chemical Vapor Deposition of Titanium Silicide”, by Maa et al., published in J. Vac. Sci. Technol. B 17(5), Sep./Oct. 1999, pp 2243-2247.
Article entitled, “Effects on Selective CVD of TITanium Disilicide by Substrate Doping and Selective Silicon Deposition”, by Maa et al., published in Mat. Res. Soc. Symp. Proc. vol. 564, pp. 85-89.
Article entitled, “Prevention of Corner Voiding in Selective CVD Deposition of Titanium Silicide on SOI Device”, by Maa et al., published in Mat. Res. Soc. Symp. Proc. vol. 564, pp 29-34.
Article entitled, “Selective Deposition of TiSi2on Ultra-Thin Silicon-On-Insulator (SOI) Wafers”, by Maa et al., published in Thin Solid Films 332(1998) pp. 412-417.

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