Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-04-18
2002-06-11
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S254000
Reexamination Certificate
active
06403418
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a method of fabricating the capacitors of dynamic random access memory (DRAM) cells, and more particularly to the cup-shape cylindrical capacitor structure of high density DRAMs.
(2) Description of the Related Art
A DRAM cell comprises a metal-oxide-semiconductor field effect transistor (MOSFET) and capacitors which are built in a semiconductor silicon substrate. There is an electrical contact between the source of a MOSFET and the storage node of the adjacent capacitor, forming a memory cell of the DRAM device. A large number of memory cells make up the cell arrays which combine with the peripheral circuit to produce DRAMs.
In recent years, the sizes of the MOSFETs and capacitors have become continuously smaller so that the packing densities of these DRAM devices have increased considerable. For example, a number of semiconductor manufacturing companies in the world have already begun mass production of 16 M bit or even 64 M bit DRAMs.
As the sizes of the capacitors become smaller, so that the capacitance values of the capacitors are decreasing, that reduces the signal to noise ratio of the DRAM circuits, causing the performance problem. The issue of maintaining or even increasing the surface area of the storage nodes or reducing the thickness of the dielectric layer is particularly important as the density of the DRAM arrays continues to increase for future generations of memory devices.
When the capacitor is used to fabricate 16 Mbit DRAMs and beyond, increasing the capacitor surface area becomes a top priority. Various shapes of capacitor structures have been used to address this issue. U.S. Pat. No. 5,185,282 to Lee et al. (the entire disclosure of which is herein incorporated by reference) provides a method of fabricating cup-shaped capacitor storage node. Another U.S. Pat. No. 5,021,357 to Taguchi et al. (the entire disclosure of which is herein incorporated by reference) discloses a method of fabricating fin structure capacitor electrode. These capacitor structures can effectively increase the capacitance values of the capacitors, however, these processes are too complicated and highly fastidious. They are difficult to be practically employed for DRAM mass-production.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the present invention to provide a method for fabricating a DRAM cell fabrication with greater capacitance per unit area.
It is another object of the present invention to provide a method of fabricating the stack capacitor structure of the high density DRAMs.
It is a further object of the present invention to provide an easy and manufacturable process for high density DRAMs that can reduce the processing steps and fabrication cost.
These objects are accomplished by the fabrication process described below.
First, a field oxide layer for isolation is grown on the semiconductor silicon substrate by standard integrated circuit fabrication process. Then, bitlines and MOSFET regions which include gate oxides, gate electrodes and source/drain regions are formed on the semiconductor silicon substrate.
Next, a first dielectric and a second dielectric layers are sequentially deposited. The first dielectric layer is planarized and the first and second dielectric layers are then etched by plasma-etching to expose the source regions of the MOSFET in order to form cell contact windows of the DRAMs.
Then, the first polysilicon layer which is overlaying the second dielectric layer and filling into the cell contacts is formed. The next step is the key point of the present invention, a third dielectric layer is formed overlaying the first polysilicon layer, and defined into third dielectric crowns by the conventional lithography and etching techniques.
Next, a second polysilicon layer is deposited overlaying the third dielectric crowns and first polysilicon layer. The first polysilicon and second polysilicon layers are then vertically anisotropically etchback to define storage nodes of the cylindrical capacitors. Therefore, the third dielectric crowns are removed by hydrofluoric acid (HF).
Finally, the capacitor dielectric layer and the polysilicon top plate of the capacitor are formed by standard integrated circuit technologies. Therefore, the cup shape cylindrical capacitor for high density DRAM applications is accomplished.
REFERENCES:
patent: 5436187 (1995-07-01), Tanigawa
patent: 5580813 (1996-12-01), Hachisuka et al.
patent: 5629225 (1997-05-01), Iwakiri et al.
patent: 5688726 (1997-11-01), Kim
patent: 5691229 (1997-11-01), Okamura et al.
patent: 6096597 (2000-08-01), Tsu et al.
Cheng Jia-Shyong
Hsieh Ming-Teng
Jen Tean-Sen
Wang Shiou-Yu
Bacon & Thomas
Nanya Technology Corporation
Tsai Jey
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