Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2008-04-08
2008-04-08
Lebentritt, Michael (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S199000, C257SE21092, C257SE21431
Reexamination Certificate
active
11157521
ABSTRACT:
In a method of fabricating a CMOS transistor, and a CMOS transistor fabricated according to the method, the characteristics of first and second conductivity type MOS transistors are both simultaneously improved. At the same time, the fabrication process is simplified by reducing the number of masks required. The method includes amorphizing the active region of only the second conductivity type MOS transistor, and performing selective etching to form a first recessed region of a first depth in the active region of the first conductivity type MOS transistor and a second recessed region of a second depth that is greater than the first depth in the active region of the second conductivity type MOS transistor. Selective epitaxial growth is performed in the first and second recessed regions to form an elevated epitaxial layer that fills the first recessed region and extends to a level that is above the upper surface of the semiconductor substrate and to form a recessed epitaxial layer that fills the second recessed region.
REFERENCES:
patent: 5834810 (1998-11-01), Schunke et al.
patent: 6605498 (2003-08-01), Murthy et al.
patent: 6987061 (2006-01-01), Mehrotra
patent: 7045407 (2006-05-01), Keating et al.
patent: 7078285 (2006-07-01), Suenaga
patent: 7118952 (2006-10-01), Chen et al.
patent: 7151034 (2006-12-01), Lee et al.
patent: 7166897 (2007-01-01), Orlowski et al.
patent: 7195985 (2007-03-01), Murthy et al.
patent: 7262472 (2007-08-01), Pidin
patent: 7288448 (2007-10-01), Orlowski et al.
patent: 2002/0109135 (2002-08-01), Murota et al.
patent: 2003/0080361 (2003-05-01), Murthy et al.
patent: 2005/0164450 (2005-07-01), Fang et al.
patent: 2005/0287752 (2005-12-01), Nouri et al.
patent: 2006/0088968 (2006-04-01), Shin et al.
patent: 2006/0166492 (2006-07-01), Orlowski et al.
patent: 2007/0099369 (2007-05-01), Ning
patent: 2002-0066191 (2002-08-01), None
Chang, G. K. “Selective Etching of SiGe on SiGe/Si Heterostructures” Journal of the Electrochemical Soc. vol. 138 No. 1 Jan. 1991 p. 202-204.
Welser, J., et al. “Strain Dependence of the Performance Enhancement in Strained-Sin-MOSFETs.” IEDM Tech. Dig. 1994, p. 373.
Rim, K., et al. “Enhanced Hole Mobilities in Surface-channel Strained-Sip-MOSFETs.” IEDM Tech. Dig. 1995, p. 517.
Lee Ho
Lee Seung-hwan
Rhee Hwa-sung
Shin Dong-suk
Tetsuji Ueno
Mills & Onello LLP
Withers Grant S
LandOfFree
Method of fabricating CMOS transistor and CMOS transistor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating CMOS transistor and CMOS transistor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating CMOS transistor and CMOS transistor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3949151