Method of fabricating CMOS semiconductor device

Details Method of fabricating CMOS semiconductor device Method of fabricating CMOS semiconductor device

1999-08-25

2000-10-17

Fahmy, Wael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438199, 438223, 438231, 438217, H01L 218238

Patent

active

061330825

ABSTRACT:
A method of fabricating a CMOS semiconductor device is provided, which decreases the number of necessary photolithography processes for forming the LDD and pocket structures. A first pair of doped regions of a first conductivity type are formed in a first section of a semiconductor substrate and a second pair of doped regions of the first conductivity type are formed in a second section thereof. Then, a third pair of doped regions of a second conductivity type are formed in the first pair of doped regions and a fourth pair of doped regions of the second conductivity type are formed in the second pair of doped regions. Thereafter, an impurity of the second conductivity type is selectively ion-implanted into the first section while covering the second section with a mask, thereby forming a fifth pair of doped regions of the second conductivity type from the first pair of remaining doped regions. Further, another impurity of the first conductivity type is selectively ion-implanted into the first section while the second section is covered with the mask, thereby forming a sixth pair of doped regions of the first conductivity type from the second pair of doped regions. The channeling effect of an implanted impurity may be utilized, where a pair of doped regions in one of the first and second sections are formed deeper than another pair of doped regions in the other.

REFERENCES:
patent: 5217910 (1993-06-01), Shimizu et al.
patent: 5716861 (1998-02-01), Moslehi
patent: 5770494 (1998-06-01), Yamamoto
L. Su et al., "High-Performance 0.08 .mu.m CMOS", Symposium on VLSI Technology Digest of Technical Papers, (1996), pp. 12-13 with Abstract.
A. Ono et al., "Suppression of V .sub.th fluctuation by minimizing transient enhanced diffusion for deep sub-quarter micron MOSFET", IEDM Technical Digest, (1996), pp. 755-758 with Abstract.
S. Ohkawa et al., "Thermal Oxidation of Arsenic-Diffused Silicon", Journal of Electrochemical Society, (Dec. 1978), pp. 1997-2002 with Abstract.

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