Method of fabricating CMOS devices with ultra-shallow junctions

Details Method of fabricating CMOS devices with ultra-shallow junctions Method of fabricating CMOS devices with ultra-shallow junctions

1997-02-10

2000-01-18

Booth, Richard

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438564, H01L 21336, H01L 2122, H01L 2138

Patent

active

060157402

ABSTRACT:
A method of making a semiconductor device forms a gate on a substrate and provides a self-aligned diffusion source on the substrate, without the use of a mask. The diffusion source provides dopant material into the substrate. The self-aligning of the diffusion source avoids misalignment of the mask and improper doping. When the diffusion source is polysilicon or amorphous silicon, subsequent patterning and siliciding of the polysilicon forms silicided interconnect straps available for interconnecting devices on the semiconductor wafer.

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G.E. Georgiou, T.T. et al., "Shallow Junctions by Out-Diffusion from BF.sub.2 Implanted Polycrystalline Silicon", J. Appl. Phys. 68(7), pp. 3707-3713, Oct. 1, 1990.

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