Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-06-30
2001-10-16
Bowers, Charles (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S216000, C438S218000, C438S221000, C438S229000, C438S230000, C438S231000, C438S233000, C438S585000, C438S588000, C438S591000, C438S592000, C438S595000
Reexamination Certificate
active
06303418
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to fabricate complementary metal oxide semiconductor, (CMOS), device, featuring dual gate structures, such as a metal gate as well as a metal-polysilicon gate, on an underlying high dielectric constant, (high k), gate insulator layer.
(2) Description of Prior Art
Integrated circuit, (IC), technology has progressed to the point in which two different gate insulator thicknesses have been used to create CMOS devices with two different threshold voltages, allowing different, desired operating voltages to be realized for each CMOS device. Subsequent CMOS development featured gate structures, each comprised of a specific metal, on an underlying high k gate insulator, with each CMOS device resulting in a specific threshold, or operating voltage, realized via the difference in work function supplied by each specific metal. However the use of two different metal gate structures results in an increase in process complexity, as well as an increase in fabrication costs. In addition the use of polysilicon gate structures, on various thicknesses of underlying gate insulator layer, can result in CMOS device depletion effects resulting especially from N type implanted, polysilicon gate structures, when formed on thin silicon dioxide gate insulator layers.
This invention will describe a novel fabrication procedure for CMOS devices, in which dual gate structures, a metal gate, as well as a metal-polysilicon gate structure, are formed on an underlying high k gate insulator layer, resulting in a specific threshold voltage for each specific gate structure. Prior art, such as Liao et al, in U.S. Pat. No. 5,480,839, describe a method of fabricating CMOS devices that operate at different voltages, resulting from the use of doped, as well as undoped, polysilicon gate structures. However that prior art does not describe the unique process sequence of the present invention, in which metal gate structures, as well as metal-polysilicon gate structures, are formed on an underlying, thin high k gate insulator layer allowing a specific operating voltage to be realized for a CMOS device, as a function of structure type.
SUMMARY OF THE INVENTION
It is an object of this invention to fabricate CMOS devices on a semiconductor substrate, featuring a first set of CMOS devices, operating at a first voltage, and featuring a second set of CMOS devices, operating at a second voltage.
It is another object of this invention to use a high k gate insulator layer for both the first set, and the second set of CMOS devices.
It is still another object of this invention to form metal-polysilicon gate structures for the first set of CMOS devices, while using metal gate structures for the second set of CMOS devices.
It is still yet another object of this invention to simplify the whole process of making dual gate CMOS devices
In accordance with the present invention of a method of fabricating a first set of CMOS devices, designed to operate at a first voltage, and fabricating a second set of CMOS devices, designed to operate at a second voltage, is described. Silicon nitride, dummy gate structures are formed in a first region of a semiconductor substrate, to be used for a P channel, (PMOS), CMOS devices, and silicon nitride dummy gate structures are also formed in a second region of the semiconductor substrate, to be used for an N channel, (NMOS), CMOS devices. After formation of P type, lightly doped source/drain, (LDD) regions, insulator sidewall spacers, and P type, heavily doped source/drain region, in the first region, or PMOS region of the semiconductor substrate, N type LDD regions, insulator sidewall spacers, and N type, heavily doped source/drain regions are formed in the second region, or NMOS region of the semiconductor substrate. Deposition of a composite insulator layer is followed by a chemical mechanical polishing, (CMP), procedure, resulting in exposure of the top surface of the silicon nitride dummy gate structures, embedded in the composite insulator layer. After selective removal of the silicon nitride dummy gate structures, a high k gate insulator layer is deposited, followed by the deposition of an in situ doped, polysilicon layer. Photolithographic, and wet etching procedures are used to remove polysilicon from the top surface of the high k gate insulator layer, in the second, or NMOS region, still leaving polysilicon on the high k gate insulator layer, in the first, or PMOS region. Deposition of a metal layer, on polysilicon, fills the space vacated by the silicon nitride dummy structures, in the PMOS region, while the same metal deposition fills the space vacated by the silicon nitride dummy gate structures, in the NMOS region. Another CMP procedure removes the metal layer from the top surface of the high k layer in a region in which the high k layer resided on the top surface of the composite insulator layer, resulting in: metal-polysilicon gate structures on the high k gate insulator layer, embedded in the composite insulator layer in a first, or PMOS region of the semiconductor substrate, and metal gate structures on the high k gate insulator layer, embedded in the composite insulator layer in a second, or NMOS region of the semiconductor substrate.
REFERENCES:
patent: 5112765 (1992-05-01), Cederbaum et al.
patent: 5480830 (1996-01-01), Liao et al.
patent: 5731239 (1998-03-01), Wong et al.
patent: 5960270 (1999-09-01), Misra et al.
patent: 5966597 (1999-10-01), Wright
patent: 6033963 (2000-03-01), Huang et al.
patent: 6200866 (2001-03-01), Ma et al.
Cha Cher Liang
Chan Lap
See Alex
Bowers Charles
Chartered Semiconductor Manufacturing Ltd.
Gurley Lynne
Pike Rosemary L. S.
Saile George O.
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