Method of fabricating capacitors of a memory cell array

Details Method of fabricating capacitors of a memory cell array Method of fabricating capacitors of a memory cell array

1998-06-05

2001-07-31

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S244000, C438S254000, C438S387000, C438S396000, C438S397000

Reexamination Certificate

active

06268244

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating capacitors of a semiconductor memory cell array and, more particularly, to a method of fabricating storage capacitors of the memory cells of a dynamic random access memory (DRAM).
2. Discussion of the Related Art
The heart of current DRAM technology is the one-transistor memory cell, which consists of a single storage capacitor connected to a single access transistor connected to a bit-line and a word-line. The word-line controls the movement of a bit of information into and out of the memory cell, and the bit-line transmits that bit of information to the system within which the memory cell is included. The information to be retained by the memory cell is represented by the charge stored on the capacitor; the access transistor gates that charge onto the bit-line.
The storage capacitor is the primary focus in the design of a DRAM. The fundamental challenge of DRAM design is the compromise between the conflicting needs for a physically small memory cell (small lateral area) and an electrically large storage capacitor (large capacitance). Minimizing the lateral area of the memory cells (i.e., the area subtended on the surface of the substrate by the cells) is important because there are so many memory cells per DRAM one cell per bit stored. For most DRAMs, 50-60% of the die area of the device consists of memory cells. Larger memory cells result in larger, more expensive DRAM dies. Maximizing the capacitance of the storage capacitor is important because capacitors having larger capacitance store more charge at a given voltage. Reading the bit of information stored in a memory cell involves dividing the charge stored on the storage capacitor between the parasitic capacitance of the bit-line and the capacitance of the storage capacitor. If the ratio of the bit-line capacitance to the storage capacitance is too large, then detecting the impact of the storage capacitor or the bit-line would be slowed, more difficult, and more error prone.
The capacitance of a capacitor may be increased either by increasing the dielectric constant of the insulator between the plates of the capacitor or by increasing the ratio of the effective area of the plates to the effective separation between the plates. Although research is continuing into the use of different materials (e.g., tantalum pentoxide, which has a significant higher dielectric constant than silicon dioxide) as the insulator between the plates of the storage capacitor, novel storage capacitor structures, rather than novel materials, currently appear to offer the most promising route to increasing capacitance while reducing effective memory cell size. Storage capacitors whose plates a have fin-shaped or cylinder-shaped structures have been used with mixed results in achieving this goal.
Process steps used in a conventional method of fabricating the storage capacitors of a DRAM array are described immediately below with reference to the idealized cross-sectional views of
FIGS. 1A-1M
.
As illustrated in
FIG. 1A
, the information of thick field oxides
2
using a conventional LOCOS process defines active and field regions of a semiconductor substrate
1
. Gate electrode structures
3
are formed on the active regions of the substrate, and cap/sidewall oxides
4
are formed on the gate electrode structures. After BoroPhosphoSilicate Glass (hereinafter BPSG) has been deposited over the substrate (i.e., on exposed surfaces of structures that have been formed on the substrate and on exposed areas of the substrate that have not been covered by the structures), annealed, and planarized, a bit-line contact hole
6
is formed between members of each of adjacent gate electrode structures
3
using well-known photolithographic and etching processes, thereby forming a first BPSG layer
5
. As illustrated in
FIG. 1B
, a doped first polysilicon layer
7
is then formed on the first BPSG layer
5
and within the bit-line contact hole
6
. A refractory metal silicide layer
8
is formed at the surface of the first polysilicon layer
7
. Photoresist is spun onto the silicide layer
8
and formed by conventional process steps into a first photoresist pattern PR
1
, which masks the portion of the silicide layer
8
positioned above the bit-line contact hole.
As shown in
FIG. 1C
, the first polysilicon layer
7
and the silicide layer
8
, masked by the first photoresist pattern PR
1
, are etched in order to form a polysilicon bit-line precursor
7
a
and a silicide
8
a,
respectively, which together comprise a bit-line.
As shown in
FIG. 1D
, after the photoresist pattern PR
1
has been stripped, a first High temperature, Low pressure Dielectric (hereinafter HLD) layer
9
is formed over the substrate.
As illustrated in
FIG. 1E
, a first nitride film
10
of thickness of 110-200 Å is deposited onto the first HLD layer
9
. BPSG is deposited onto the nitride film
10
, annealed, and etched-back in order to form a planar second BPSG layer
11
. A second HLD layer
12
is formed on the second BPSG layer
11
. Photoresist is spun onto the second HLD layer
12
and formed, using conventional process steps, into a second photoresist pattern PR
2
. The second photoresist pattern PR
2
masks the second HLD layer above the bit-lines, the gate electrode structures, and the field oxides.
As illustrated in
FIG. 1F
, the first BPSG layer
5
, the first HLD layer
9
, the first nitride film
10
, the second BPSG layer
11
, and the second HLD layer
12
are masked by the second photoresist pattern PR
2
, are anisotropically etched in order to form note contact holes
13
, thereby forming an etched first BPSG layer
5
a,
an etched first HLD layer
9
a,
an etched first nitride film
10
a,
an etched second BPSG layer
11
a,
and an etched second HLD layer
12
a,
respectively. After the second photoresist pattern PR
2
has been striped, source/drain regions of the MOS transistors of the memory cells are formed within the substrate by diffusion of dopants through the areas of the surface of the substrate that have been exposed by formation of the node contact holes
13
.
As illustrated in
FIG. 1G
, insulating sidewalls
14
are formed on either side of each of the node contact holes
13
.
As illustrated in
FIG. 1H
, a doped second polysilicon layer
15
is formed on the etched second HLD layer
12
a
and within the node contact holes
13
. An Undoped Silicate Glass (hereinafter USG) layer
16
is deposited onto the second polysilicon layer
15
. Photoresist is spun onto the USG layer
16
and formed by conventional process steps into a third photoresist pattern, PR
3
, which masks the USG layer above the node contact holes.
As illustrated in
FIG. 1I
, the second polysilicon layer
15
and the USG layer
16
, masked by the third photoresist pattern PR
3
, are etched back to form doped polysilicon charge storage structures
15
a
and (insulating) USG caps
16
a,
respectively, an insulating cap atop each of the conductive charge storage structures.
After the third photoresist pattern PR
3
has been stripped, a doped third polysilicon layer
17
is formed over the substrate, as illustrated in FIG.
1
J.
As illustrated in
FIG. 1K
, the third polysilicon layer
17
is etched back until regions of the etched second HLD layer
12
a
are exposed, thereby forming doped polysilicon additions
17
a
contiguous to either side of each of the (conductive) polysilicon charge storage structures
15
a,
thereby completing the formation of first polysilicon plate nodes
18
. A first plate node
18
comprises a charge storage structure
15
a
and the pair of additions
17
a
contiguous to, and in electrical continuity with, either side of each of the charge storage structures.
As illustrated in
FIG. 1L
, the USG caps
16
a,
the etched second HLD layer
12
a
and the etched second BPSG layer
11
a
are removed by wet-etching the nitride layer
10
a
serving as an etch stop.
As illustrated in
FIG. 1M
, a dielectric film
19
is deposited over the substrate and a do

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