Method of fabricating capacitors

Details Method of fabricating capacitors Method of fabricating capacitors

2000-08-11

2001-03-27

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S393000

Reexamination Certificate

active

06207495

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention related to a method of fabricating capacitors which fabricates a plurality of capacitors of which capacitances are different one another on a semiconductor substrate.
2. Discussion of Related Art
In semiconductor devices, a memory device requires capacitors of which sizes are large for storing a lot of data. Thus, effective area for capacitance is increased by forming a three-dimensional structure such as the stacked, the trench-typed structure and the like to store large amount of data as well as the area occupied by an unit cell is reduced.
However, logic devices change impedance constantly according to frequencies of inputted signals which are operated by the signals which are constituted by digital and analog signals, thereby requiring no such capacitors as have large capacitance. Therefore, capacitors in logic devices are formed two-dimensionally on field oxide layers defining active areas of the devices.
FIG. 1A
to
FIG. 1C
show cross-sectional views of fabricating a capacitor according to a related art.
Referring to
FIG. 1A
, a field insulating layer
13
forming an active area of a device is formed in a field area on a semiconductor substrate
11
. In this case, the field insulating layer
13
is formed by LOCOS(local oxidation of silicon) or STI(shallow trench isolation).
A first polysilicon layer
15
is formed on the semiconductor substrate
11
to cover the field insulating layer
13
by depositing polysilicon doped with impurities by CVD(hereinafter abbreviated CVD). And, a dielectric layer
17
having an ONO structure is formed by depositing silicon oxide, silicon nitride, and silicon oxide on the first polysilicon layer
15
successively by CVD. Referring to
FIG. 1B
, the dielectric layer
17
and first polysilicon layer
15
are patterned to expose the semiconductor substrate
11
and field insulating layer
13
by photolithography. In this case, the polysilicon layer
15
and the dielectric layer
17
which are not etched but remain become a lower electrode
16
of a capacitor and a dielectric, respectively.
A second polysilicon layer
18
is formed on the semiconductor substrate
11
by depositing polysilicon doped with impurities to cover the field insulating layer
13
, lower electrode
16
, and dielectric layer
17
by CVD.
Referring to
FIG. 1C
, an upper electrode
19
is formed by patterning the second polysilicon layer
18
only to remain on the dielectric layer
17
to expose the semiconductor substrate
11
and field insulating layer
13
by photolithography. Thus, the upper electrode
19
constitutes a capacitor with the lower electrode
16
and dielectric layer
17
.
As mentioned in the above description, the related art fabricates a capacitor by forming a first polysilicon layer and a dielectric layer on a semiconductor substrate to cover a field insulating layer in order, by forming a lower electrode by means of patterning the layers by photolithography, by forming a second polysilicon layer on the semiconductor substrate to cover the lower electrode and dielectric layer, then by forming an upper electrode by means of patterning the second polysilicon layer to remain on the dielectric layer by photolithography.
Unfortunately, it is difficult to fabricate a plurality of capacitors of various capacitances on the same substrate in the related art because thickness of the dielectric layer is uniform.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method of fabricating capacitors that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
The object of the present invention is to provide a method of fabricating capacitors which enables to fabricate a plurality of capacitors of which capacitances are various on the very substrate. Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention includes the steps of forming a field insulating layer providing an active area of a device in a field area on a semiconductor substrate, forming a first polysilicon layer and a first dielectric substance layer on the semiconductor substrate successively to cover the field insulating layer, forming a first dielectric layer over one stage of the field insulating layer by patterning the first dielectric substance layer, forming a second dielectric substance layer to cover the first dielectric layer on the first polysilicon layer, forming a first lower electrode and a second dielectric layer over the stage of the field insulating layer as well as forming a second lower electrode and the second dielectric layer over the other stage of the field insulating layer by patterning the second dielectric substance layer and the first polysilicon layer wherein the first dielectric layer is inserted between the first lower electrode and the second dielectric layer, forming a second polysilicon layer on the second dielectric layer, and forming a first and a second upper electrode by patterning the second polysilicon layer.
In another aspect, the present invention includes the steps of forming a field insulating layer providing an active area of a device in a field area on a semiconductor substrate, forming a first polysilicon layer and a first dielectric substance layer successively on the semiconductor substrate to cover the field insulating layer, forming a first dielectric layer over one stage of the field insulating layer by patterning the first dielectric substance layer, forming a second dielectric substance layer and a second polysilicon layer to cover the first dielectric layer successively on the first polysilicon layer, forming a common lower electrode by patterning the second polysilicon layer, second dielectric substance layer, and first polysilicon layer just to remain over the field insulating layer wherein the common lower electrode is defined the remaining first polysilicon layer, forming a second dielectric layer and a first upper electrode on one stage of the common lower electrode as soon as forming a second dielectric layer and a second upper electrode on the other stage of the common lower electrode by patterning the second polysilicon layer and second dielectric substance layer to expose a middle part of the common lower electrode wherein the first dielectric layer is inserted between the second dielectric layer and the common lower electrode. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 6096600 (2000-08-01), Azami
patent: 6146906 (2000-11-01), Inoue et al.

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