Method of fabricating capacitor

Details Method of fabricating capacitor Method of fabricating capacitor

1998-12-29

2001-04-24

Le, Vu A. (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S240000, C438S253000, C438S254000, C438S396000

Reexamination Certificate

active

06221710

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a semiconductor device fabrication. More particularly, the present invention relates to a method of fabricating a capacitor.
2. Description of Related Art
Polysilicon is commonly used as an electrode for a capacitor in a semiconductor device fabrication. However, an electrode made from polysilicon still has many disadvantages such as depletion occurring in the polysilicon electrode. The depletion causes instability of the capacitor's capacitance so as to decrease the performance of devices.
FIG. 1
is a schematic, cross-sectional view showing a conventional method of fabricating a capacitor. As shown in
FIG. 1
, a semiconductor substrate
101
is provided. A polysilicon layer
107
is formed over the substrate
101
. The polysilicon layer
107
is a part of a structure preformed over the substrate
101
. A dielectric layer
105
is formed over the substrate
110
. A tungsten plug
103
is formed in the dielectric layer
105
. A barrier/glue layer
108
is formed between the tungsten plug
103
and the dielectric layer
105
to increase adhesion between the metal plug
103
and the dielectric layer
105
.
Another barrier/glue layer
109
is formed over the substrate
101
to cover the metal plug
103
. A polysilicon layer
111
is formed on the barrier/glue
109
to serve as a bottom electrode of a capacitor formed subsequently. A dielectric layer
113
made EXPRESS MAL NO. from oxide is formed on the polysilicon layer
115
. Another polysilicon layer
115
is formed on the dielectric layer
113
to serve as an upper electrode. A complete capacitor is formed.
In the conventional method, some ions such as phosphorous ions or arsenic ions are doped into the polysilicon layer which serves as the bottom electrode of the capacitor in order to increase conductivity. However, when a voltage is applied to the upper electrode of the capacitor, inductive charges are generated. Thus, the inductive charges generated at the interfacial between the bottom electrode and the dielectric layer are neutralized with the dopants of the polysilicon layer so as to form a depletion region in the bottom electrode.
As shown in
FIG. 2
,
FIG. 2
is a schematic, cross-sectional view of what happens when a voltage is applied to a conventional capacitor. A capacitor
120
is composed of polysilicon layers
117
,
119
and a dielectric layer
121
. When a negative voltage is applied to an upper electrode
117
of the capacitor
120
, inductive positive charges are generated in a bottom electrode
119
of the capacitor
120
. At this time, a part of the inductive positive charges is neutralized with the dopants of the polysilicon layer so as to form a depletion region
123
at the interface between the bottom electrode
119
and the dielectric layer
121
.
The depletion region
123
is viewed as a dielectric layer. In other words, the dielectric layer
121
is thickened due to the depletion region
123
. The thickness of the dielectric layer
121
is increased. Since the charge-storing ability of the capacitor is relative to the thickness of the dielectric layer, the thinner the dielectric layer is, the greater the capacitance of the capacitor. The depletion region causes an increase in the thickness of the dielectric layer, in other words, the capacitor's capacitance is lowered so as to reduce performance of devices. Moreover, as different voltages are applied to the capacitor, the thickness of the depletion region
108
is changed. The voltage coefficient (1/C(dC/dV)) of the capacitor is thus increased so that the capacitance of the capacitor is changed as the different voltages are applied. Thus, stability of devices is decreased.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a method of fabricating a capacitor. The method not only simplifies the process but also avoids a depletion region generated in a polysilicon electrode as seen in a conventional method, which causes a decrease in a capacitor's capacitance. Thus, performance of devices is increased.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of fabricating a capacitor. A semiconductor substrate is provided. A barrier layer is formed over the substrate to serve as a bottom electrode of the capacitor. A dielectric layer is formed on the barrier layer. An upper electrode is formed on the dielectric layer. In addition, the method can be used in a dynamic random access memory.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5330931 (1994-07-01), Emesh et al.
patent: 5516719 (1996-05-01), Ryou
patent: 5834357 (1998-11-01), Kang
patent: 6057189 (2000-05-01), Huang et al.

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