Method of fabricating buried source to shrink cell dimension and

Details Method of fabricating buried source to shrink cell dimension and Method of fabricating buried source to shrink cell dimension and

1998-05-06

2000-01-25

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438265, 438266, H01L 218247

Patent

active

060177950

ABSTRACT:
A method is provided for forming a split-gate flash memory cell having reduced size, partially buried source line, increased source coupling ratio, improved programmability, and overall enhanced performance. A split-gate cell is also provided with reduced size and improved performance. The source line is formed in a trench in the substrate over the source region. The trench walls provide increased source coupling and the absence of gate bird's beak with the trench together shrink the cell size. Programmability is also enhanced through more favorable hot electron injection though intergate oxide between the floating gate and the control gate.

REFERENCES:
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patent: 5527727 (1996-06-01), Kim
patent: 5627393 (1997-05-01), Hsu
patent: 5915178 (1999-06-01), Chiang et al.

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