Method of fabricating BiCMOS devices

Details Method of fabricating BiCMOS devices Method of fabricating BiCMOS devices

1997-10-22

1998-12-22

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438202, H01L 744

Patent

active

058518649

ABSTRACT:
A BiCMOS process which provides both low voltage (digital) and high voltage (analog) CMOS devices. The high voltage NMOS devices have a compensated drain formed by the NPN and PNP base implants. The PNP base plus the high voltage NMOS drain carrier concentrations are both optimized by adjustment of the two variables N base implant dose and P base implant dose; this determines the NPN base carrier concentration which turns out to provide good NPN characteristics. Low voltage NMOS source and drain implants employ a higher dose and may also be used for the high voltage NMOS source. The NPN emitter doping may also be used for a contact to the high voltage NMOS drain contact.

REFERENCES:
patent: 5119162 (1992-06-01), Todd et al.
patent: 5148255 (1992-09-01), Nakazato et al.
patent: 5169794 (1992-12-01), Iranmanesh
patent: 5216271 (1993-06-01), Takagi et al.

Affiliated with

Also associated with

Rating

Method of fabricating BiCMOS devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating BiCMOS devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating BiCMOS devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2046660