Semiconductor device manufacturing: process – Radiation or energy treatment modifying properties of... – By differential heating
Reexamination Certificate
2002-12-20
2004-11-16
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Radiation or energy treatment modifying properties of...
By differential heating
C438S795000, C438S796000, C117S003000
Reexamination Certificate
active
06818569
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating an annealed wafer and, more particularly, to a method of fabricating an annealed wafer of high quality by forming a defect-free active region of a device and controlling an irregular resistivity characteristic.
2. Background of the Related Art
Generally, a silicon wafer is prepared by growing a single crystalline silicon ingot and forming a wafer therefrom through slicing, etching, and polishing processes carried out on the single crystalline silicon ingot. Grown-in defects generated from growing the single crystalline silicon are eliminated from the silicon wafer in order to provide a device active region that is free of defects as well as form a highly concentrated oxygen defect layer in the silicon wafer, for which high temperature annealing is essentially carried out at about at least 1,200° C. for a predetermined time in an Ar ambience. Yet, if the high temperature annealing is carried out in the Ar ambience, as shown in
FIG. 1
, boron (B) atoms
20
are absorbed in the surface of the silicon wafer
10
when left in a clean room for a predetermined time. The boron atoms penetrate the silicon wafer
10
while a high thermal treatment is carried out at about 1,200° C. for a predetermined time in the ambience of Ar gas in the course of annealing the silicon wafer. Namely, as shown in
FIG. 2
, the concentration b of boron reaches a maximum level at the surface of the silicon wafer, and the concentration b of the boron atoms becomes irregular due to the diffusion of the boron atoms from the surface of the silicon wafer to a depth therein of about 5 &mgr;m. Hence, a minimum resistivity a of the silicon wafer exists at the surface of the silicon wafer, and becomes irregular from the surface of the silicon wafer to a depth therein of about 5 &mgr;m.
In order to overcome such a problem, the related art uses a method of re-polishing the surface of an annealed wafer or a HF-cleaning method of eliminating boron atoms by cleaning the silicon wafer with HF solution right before high temperature annealing in an Ar gas ambience. However, the re-polishing method grinds the irregular resistivity layer to leave a uniform resistivity layer only, whereby a denuded zone (DZ) and a COP-free region are reduced in thickness. Hence, it is difficult to provide a product that meets user's specification. Regarding the characteristics of the boron concentration b and resistivity a of the annealed wafer on which Ar annealing is carried out after the HF-cleaning, as shown in
FIG. 3
, such characteristics seem to be very uniform, but contamination of the HF solution may occur in such a case. Hence, an ultra-pure HF solution is required. Besides, additional processes such as re-polishing, HF cleaning, and the like are further carried out as well as the annealing, thereby increasing the product cost.
Japanese Patent Laid-Open Publication No. P2002-100634A (Apr. 5, 2002) proposes a solution overcoming the problem of the related art. It teaches that high temperature annealing is carried out in Ar gas after thermal treatment is carried out using a mixed gas of H
2
and Ar. Yet, if a concentration of H
2
gas exceeds a predetermined quantity to be mixed with oxygen, explosion may occur. Hence, the method disclosed by Japanese Patent Laid-Open Publication No. P2002-100634A mixes H
2
with Ar as inert gas. In this case, a concentration rate of H
2
is limited to an amount below about 3-4%. Since the concentration of H
2
is extremely small to mix, the silicon wafer should be annealed for a long time. Hence, an efficiency of the annealing process for fabricating the annealed wafer is reduced.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method of fabricating an annealed wafer that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
The object of the present invention is to provide a method of fabricating an annealed wafer of high quality, which has a uniform resistivity due to a uniform boron concentration in the surface of a defect-free silicon wafer, enabling annealing efficiency of the silicon wafer to be improved as well as reducing product cost.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages, and in accordance with the purpose of the present invention as embodied and broadly described, a method of fabricating an annealed wafer includes a first annealing step of pre-heating a silicon wafer at a temperature of about 500° C. in a furnace in an ambience of a gas selected from the group consisting of Ar, N
2
or an inert gas including Ar and N
2
; a second annealing step of changing the ambience of the gas into a 100% H
2
gas ambience, increasing the temperature to 850° C.~1,150° C., and carrying out annealing for about an hour by maintaining the increased temperature; a third annealing step of changing the ambience of the gas into a 100% Ar gas ambience, increasing the temperature to about 1,200° C., and carrying out annealing for about an hour while a temperature of about 1,200° C. is maintained; and a temperature dropping step of decreasing the temperature in the furnace below about 500° C.
Preferably, the second annealing step includes the steps of increasing the temperature in the furnace to about 1,100° C. and carrying out the annealing for about ten minutes by maintaining the increased temperature.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 6413310 (2002-07-01), Tamatsuka et al.
patent: 6551398 (2003-04-01), Abe et al.
patent: 6566255 (2003-05-01), Ito
patent: 2002-100634 (2002-04-01), None
patent: WO 01/73838 (2001-10-01), None
Kim Gun
Mun Young-Hee
Yoon Sung-Ho
Kennedy Jennifer M.
Niebling John F.
Piper Rudnick LLP
Siltron Inc.
LandOfFree
Method of fabricating annealed wafer does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating annealed wafer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating annealed wafer will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3337378