Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-11-29
2001-07-17
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S211000, C438S217000, C438S276000
Reexamination Certificate
active
06261884
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to semiconductor devices and methods for fabricating such devices and, more particularly, to electronic memory devices and, even more particularly, to a single polysilicon flash EEPROM capable of using low programming and erasing voltages and formed of a small cell size.
BACKGROUND OF THE INVENTION
Basic input/output systems (BIOS) or microcodes are stored on memory devices such as EEPROMs and used to control microprocessors and logic circuits. Today's flexible system-on-system chip architectures require embedded EEPROMs to make possible easy updates of microcode in system configurations. However, generally, EEPROMs require special multi-polysilicon processes and multi-oxidation steps for thin SiO
2
layers. Many masks are needed which result in longer process turnaround times, lower yields, higher costs, and lower reliability.
Integration of various different semiconductor fabrication processes into one specific process generally is complicated and costly. However, K. Ohsaki, et al.,
“A Single Poly EEPROM Cell Structure for Use in Standard CMOS Processes,”
IEEE JOURNAL OF SOLID STATE CIRCUITS, Vol. 29, No. 3, March 1994, describes a single polysilicon EEPROM cell structure that may be implemented in a standard CMOS process. This structure consists of adjacently placed NMOS and PMOS transistors with an electrically isolated common polysilicon gate. The common gate works as a “floating gate” and the structure provides an inversion layer as the “control node (gate).” This EEPROM cell (the “Ohsaki Cell”) may be easily integrated with CMOS digital an analog circuits, but suffers from severe practical limitations.
Limitations associated with the Ohsaki Cell are fundamental in nature. One limitation is that it requires a high programming and erase voltage. Another limitation is that it requires a big cell size. Suffering from both of these limitations makes the Ohsaki Cell unacceptable for a simple DRAM fabrication process.
In the conventional single polysilicon EEPROM, a particular problem relates to erase techniques. One way to erase these existing structures forces a 5V level on V
D
and V
S
and forces a −6V bias on the control gate and substrate. The substrate can tie to −6V or be floating. The erase mechanism that results from this procedure is the result of diode breakdown. Unfortunately, this mechanism causes impact ionization and operates as a hole trap to the floating gate. Thus, the problem with this method is that a negative voltage is necessary and the substrate needs to float or tie to the −6V. In this method, a negative charge pump circuit is required.
There are other approaches to erasing structures such as the Ohsaki Cell. One method uses the same type of mechanism as previously described, but ties the control gate to ground. The substrate is tied to −2V and a very high voltage is forced on the drain and source. This method, unfortunately, produces very poor erase efficiency and results in too high a voltage on the source and drain. The high voltage can cause undesirable stress on the EEPROM.
The third method uses an BVCEO breakdown mechanism which causes impact ionization and a hold trap to form at the floating gate. This method, unfortunately, also has very poor erase efficiency and for many other reasons is much less desirable than the two previously described techniques.
Another limitation of the Ohsaki Cell and similar structures is the need for an N-well to serve as the control gate. This design results in a large EEPROM cell size. With the ever-important design objective of smaller memory circuits, the limitation of requiring a large cell size can seriously affect the usefulness of the single polysilicon flash EEPROM.
SUMMARY OF THE INVENTION
In light of the above-stated limitations, there is a need for an improved single polysilicon flash EEPROM that provides both low positive programming and erase voltage, as well as provides a small cell size.
The present invention, therefore, provides an improved single polysilicon flash EEPROM that overcomes or substantially eliminates the problems of programming and erase voltages, and larger cell size that adversely affect the usefulness of known single polysilicon flash EEPROMs.
According to one aspect of the present invention, there is provided a single polysilicon memory cell for use in CMOS processing and includes a P-substrate, with a P-well formed within the P-substrate, and an NMOS transistor is formed within the P-well. An N
+
control gate is also formed in the P-substrate. The NMOS transistor and the N
+
control gate have a polysilicon gate that operates as a floating gate in common with the NMOS transistor and the N
+
control gate. The N
+
control gate includes a P-channel punch-through implant region for increasing the capacitive coupling ratio. This improves the programming and erasing efficiency within said single polysilicon memory cell, thereby permitting these voltages to generally decrease.
A technical advantage of the present invention is that no additional DRAM process steps are needed to produce the reduced size EEPROM cell. Clearly, the ability to achieve this result has significant cost and throughput benefits for systems that employ the present invention.
Another technical advantage of the present invention is that it provides a smaller EEPROM cell size for minimal channel hot electron (CHE) programming voltage and minimal Fowler-Nordheim (F-N) erase voltage. Because the memory cell of the present invention does not require an N-well, as does the Ohsaki Cell, for example, it consumes less space. The result can be, therefore, that more memory cells formed according to the teachings of the present invention may be placed in a given layout area than is possible with known single polysilicon flash EEPROMs and similar devices.
Still, another technical advantage that the present invention provides is both a lower program voltage and a positive only erase voltage. For example, in one embodiment of the present invention, the maximum CHE program voltage did not exceed 5V, with the threshold voltage shift of 2.5V after CHE programming for 100 msec. In addition, this same embodiment provided a F-N erase voltage of 9V on V
DD
and V
SS
, with zero volts on V
PP
and V
BB
.
REFERENCES:
patent: 3440503 (1969-04-01), Gallagher et al.
patent: 5465231 (1995-11-01), Ohsaki
patent: 5501996 (1996-03-01), Yang et al.
patent: 5543338 (1996-08-01), Shimoji
patent: 5761121 (1998-06-01), Chang
Wellekens et al., “Single Poly Cell as the Best Choice for Radiation-hard Floating Gate EEPROM Technology”, IEEE Trans. on Nuclear Science, Dec. 1993, pp. 1619-1627.*
Adan et al., “A scaled 0.6um High Speed PLD Technology Using Single-Poly EEPROM's”, Custom Integrated Circuits Conf., 1995, IEEE Proc., pp. 55-58.*
Inokawa et al. ,“Highly Robust 0.25um Single-poly-gate CMOS with Inter-well Deep Trenches”, VLSI Tech., 1996, pp. 218-219.*
Chi et al., “A New Single-poly Flash Memory Cell with Low-voltage and Low-power Operations for Embedded Applications”, Device Research Conf. Digest, 1997, pp. 126-127.
Ho Chi-Chien
McKee William R.
Brady III Wade James
Holland Robby T.
Malsawma Lex H.
Smith Matthew
Telecky , Jr. Frederick J.
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