Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-12-08
2002-04-09
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S386000, C438S391000, C438S242000, C438S243000
Reexamination Certificate
active
06368912
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for fabricating semiconductor memory devices including random dynamic access memory (DRAM) devices. More particularly, the present invention relates to a method of fabricating an isolation structure between a vertical transistor and a deep trench capacitor.
2. Description of Related Art
As semiconductor integration continuously increases, device dimensions are necessarily accordingly decreased. Hence the conventional scaling techniques are limited by the stringent leakage requirement of devices. For a conventional DRAM cell, although the capacitor has been designed in 3 dimensions, the transistor is still designed in 2 dimensions. Therefore the integration of DRAM cell array is limited.
Grurning et al. proposed a sub-8F2 DRAM cell composing of a deep trench capacitor and a vertical transistor both in a deep trench can largely increase the integration of DRAM cells (A Novel Trench DRAM Cell with a VERtical Access Transistor and BuriEd Strap (VERI BEST) for 4 Gb/16 Gb, p25, 1999 IEDM). In sub-8F2 DRAM cell, the horizontal trench top oxide in the deep trench serves as an isolation structure between the deep trench capacitor and the vertical transistor. In general, a vertical insulating layer in a trench can be formed like a spacer, but a horizontal insulating layer in a deep trench is difficult to form.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating a horizontal isolation structure between a vertical transistor and a deep trench capacitor.
A first embodiment of this invention comprises the following steps. A substrate having a deep trench therein and in turn a pad oxide layer and a silicon nitride layer thereon is provided, wherein the deep trench has a deep trench capacitor on the bottom and an upper sidewall portion of the deep trench is exposed. An insulating layer is formed on the substrate and partially fills the deep trench by high-density plasma chemical vapor deposition. The thickness of the insulating layer on the sidewall of the deep trench is thinner than the thickness of the insulating layer on the deep trench capacitor and the substrate. The insulating layer on the sidewall of the deep trench and a certain thickness of the insulating layer on the substrate and the deep trench capacitor is removed. The thickness of the residual insulating layer, which serves as an isolation structure, on the deep trench capacitor is about 300 to about 900 Å. A certain thickness of protection layer on the insulating layer is form ed above the deep trench capacitor. The silicon nitride layer is removed by wet etching and thus the insulating layer on the silicon nitride layer is lifted. A doped region, which is on the surface of the substrate, is formed surrounding the deep trench. The pad oxide layer and the protection layer are sequentially removed. A gate oxide layer is formed on the exposed surface of the substrate. Shallow trench isolation is formed in the substrate, and the shallow trench isolation partially overlaps the deep trench. A gate is formed over the horizontal isolation and the gate oxide.
In a second embodiment, wherein the thickness of the insulating layer in the first embodiment is increased. The surface of the insulating layer is higher than the surface of the silicon nitride layer at least by about 8000 to about 10000 Å to facilitate performing chemical mechanical polishing for removing the insulating layer above the surface of the silicon nitride layer. Then the upper portion of the remained insulating layer is etched back to form the isolation structure above the deep trench capacitor.
In a third embodiment, wherein the upper portion of the insulating layer in the second embodiment is replaced by a sacrificial layer. The replacement is based on saving the high production cost of the insulating layer deposited by high-density plasma chemical deposition. The low-cost sacrificial layer is deposited by low-pressure chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition. The sacrificial layer also can be a low-cost spin-on-glass layer.
As embodied and broadly described herein, the invention provides various methods to fabricate a horizontal isolation structure between a deep trench capacitor and a vertical transistor in a deep trench. Hence the integration of DRAM cells can be largely increased by a vertical transistor and a deep trench capacitor configuration.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 6063657 (2000-05-01), Bronner et al.
patent: 6074909 (2000-06-01), Gruening
patent: 6291298 (2001-09-01), Williams et al.
Chang Chi-Han
He Tzu-En
Lee Pei-Ing
Tsai Hsin-Chuan
Baker & Botts LLP
Elms Richard
Nanya Technology Corporation
Pyonin Adam
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