Method of fabricating an insulating layer

Details Method of fabricating an insulating layer Method of fabricating an insulating layer

2002-01-29

2002-12-10

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

C438S197000, C438S152000, C438S577000

Reexamination Certificate

active

06492214

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating an insulating layer, more specifically, to a method of fabricating an insulating layer used as a mask for forming a buried bit line.
2. Description of the Prior Art
An integrated circuit typically has thousands of metal oxide semiconductor (MOS) transistors. In order to prevent short-circuiting between adjacent MOS transistors, an insulation process is used to form a field oxide (FOX) layer or a shallow trench isolation (STI) structure between adjacent MOS transistors. However, as integrated circuits become more complex and more precise, process windows become smaller as well. Consequently, the local oxidation (LOCOS) process, employed to form a field oxide layer atop a buried bit line as isolation, is no longer practical in semiconductor processes with a line width less than 0.18 microns.
Please refer to
FIG. 1
to FIG.
4
. These figures are schematic views of forming an insulating layer
22
according to the prior art. As shown in
FIG. 1
, a conductive layer
12
, a silicon nitride layer
14
, an anti-reflection coating (ARC)
16
and a cap layer
18
are formed on a surface of a semiconductor substrate
10
, respectively, to form a multi-layer structure. A photo and etching process (PEP) is then performed on the multi-layer structure to define and form at least one gate
20
.
As shown in
FIG. 2
, a first ion implantation process, using the silicon nitride layer
14
as a mask of the gate
20
, is performed to form a doped area, used as a buried bit line
21
, in portions of the silicon substrate adjacent to either side of the gate
20
. Then, a low-pressure chemical vapor deposition (LPCVD) process, using tetra-ethyl-ortho-silicate (TEOS) as a reacting gas, is performed to form an insulating layer
22
, composed of silicon oxide, thicker than a height of the gate
20
on the semiconductor substrate
10
. As the LPCVD process is performed, the insulating layer
22
follows the topography of the gate
20
to produce an uneven surface. The uneven surface has an irregular profile due to a height difference of thousands of angstroms between the gate
20
and the semiconductor substrate
10
. Thus, portions of the surface of the insulating layer
22
adjacent to either side of the gate
20
have a concave curve shape.
As shown in
FIG. 3
, a planarization process is then performed to remove portions of the cap layer
18
, the ARC
16
and the insulating layer
22
atop the gate
20
. The planarization process can be a chemical mechanical polishing (CMP) process or an etching back process, both of which use the silicon nitride layer
14
as a stop layer. Due to the planarization process, portions of the insulating layer
22
adjacent to either side of the gate
20
retain a concave curve surface shape.
As shown in
FIG. 4
, a wet etching process is performed to remove the silicon nitride layer
14
in the gate
20
, exposing the surface of the conductive layer
12
in the gate
20
. A second ion implantation process is performed to dope the conductive layer
12
so as to reduce the resistivity of the gate
20
. The insulating layer
22
is used as a mask layer of the second implantation process to prevent a penetration of ions into the buried bit line
21
, leading to a defective concentration distribution of dopants.
As shown in
FIG. 4
, a height “c” of the insulating layer
22
is greater than a height “d” of the gate
20
, as the insulating layer
22
is used as the mask layer of the doping process employed to adjust V
t
of the gate
20
. However, an effective height “a” of the mask layer, the insulating layer
22
, is determined by a concave depth “b.” Thus an irreducible concave depth “b” normally leads to a defective concentration distribution of dopants in the buried bit line
21
in the ion implantation process. Furthermore, the concave structure of the insulating layer
22
can cause cracking of the thin film layer (not shown), filled into the concave structure, in subsequent processes, leading to a decreased yield rate of the product.
SUMMARY OF INVENTION
It is therefore a primary object of the present invention to provide a method of fabricating an insulating layer with sufficient effective height so as to obtain the required concentration of dopants in a buried bit line.
It is another object of the present invention to provide a method of fabricating an insulating layer so as to prevent a concave structure leading to a cracking of a thin film layer atop the insulating layer.
According to the claimed invention, a semiconductor substrate has at least one gate, comprising at least a conductive layer and a cap oxide layer, and a bit line in portions of the semiconductor substrate adjacent to either side of the gate. An insulating layer thicker than a height of the gate on the semiconductor substrate is then formed to follow the topography of the gate to produce an uneven surface. A planar layer is then formed on the surface of the insulating layer to form an approximately flat surface for the semiconductor substrate. By performing a planarization process, a portion of the planar layer is removed down to the surface of the insulating layer. A first etching process is then performed to completely remove the remaining portions of the planar layer. Finally, a second etching process is performed to remove the insulating layer and the cap oxide layer atop the gate, so that the remaining insulating layer outside the gate has a protrusive surface after the second etching process.
It is an advantage of the present invention that a planar layer and an etching process with a predetermined selectivity are employed to remove portions of the insulating layer. The insufficient effective height of the remaining portions of insulating layer adjacent to either side of the gate is thus prevented. Consequently, the insulating layer can be a mask layer with a sufficient effective height in the subsequent implantation processes employed to adjust either a resistivity or a threshold voltage of the gate, so as to obtain the required concentration of dopants in the bit lines. Additionally, the insulating layer formed in the present invention has a protrusive surface after the second etching process. The concave structure of the insulating layer, which leads to cracking of the thin film layer in subsequent processes, is thus prevented.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the multiple figures and drawings.


REFERENCES:
patent: 6051470 (2000-04-01), An et al.
patent: 6319807 (2001-11-01), Yeh et al.

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