Method of fabricating an improved spacer

Details Method of fabricating an improved spacer Method of fabricating an improved spacer

1998-12-30

2001-08-14

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S647000, C438S648000, C438S649000, C438S651000, C438S655000, C438S664000, C438S669000, C438S778000, C427S376200, C427S376300, C427S377000

Reexamination Certificate

active

06274517

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87115246, filed Sep. 14, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention generally relates to semiconductor fabrication, and more particularly to a method of fabricating an improved spacer such as a Phoslon (PNO) spacer.
2. Description of Related Art
In general, in accordance with advances in semiconductor process techniques, the level of integration of integrated circuits increases and the channel lengths of MOS devices become shorter so that the operation speed of MOS devices may increase correspondingly. However, certain problems arise, for example short channel effects or hot electron effects, when the channel lengths of MOS devices shrink to a level.
FIG. 1
is a schematic, cross-sectional diagram showing a shifting of channel length between the source region and the drain region of a conventional MOS device, resulting from the short channel effect. As shown in
FIG. 1
, during operation of the MOS device, the source region
10
and the drain region
12
result in the depletion regions
14
and
16
respectively. The depletion regions
14
and
16
overlap part of the channel region
18
. The channel length of the MOS device changes from the longer original channel length L to the shorter effective channel length L′, as shown in FIG.
1
. As the ratio of the overlapped region (the depletion regions
14
and
16
overlap the channel region
18
) to the channel region
18
becomes larger, the effective channel length of the channel region
18
becomes shorter. If the channel length of the channel region
18
is less than approximately 1.5 &mgr;m, the channel region
18
will be electrically short and the MOS device will be always in the “ON” state. Therefore, the gate
20
of the MOS device can no longer control the MOS device.
FIG. 2
is a schematic, cross-sectional view showing electron and hole currents in a conventional MOS device resulting from the hot electron effect. The electric field (electric field=electric voltage/length) in the channel region
22
increases as the channel length of the channel region
22
shortens. As shown in
FIG. 2
, the electrons of the region
23
, which is between the channel region
22
and the drain
24
, have high energy because of the large electric field. The large electric field in the channel region
22
can accelerate the electrons of the region
23
. The electrons generated from the region
23
impact the electrons near the boundary of the drain
24
to generate lots of electron-hole pairs. Therefore, the carriers (including electrons and holes) increase to result in carrier multiplication. The electrons generating from carrier multiplication, such as electron
26
, are attracted to the drain
24
to increase the current of drain
24
. The other the electrons also generated from carrier multiplication, such as electron
27
, are injected into the gate oxide
30
. The holes generating from the carrier multiplication, such as hole
28
, enter the substrate
31
to generate substrate current. The other part of the holes generated from the carrier multiplication, such as hole
29
, are attracted to the source
32
to add to the number of hot electrons. An increase in hot electrons results in carrier multiplication and leads to the electrical breakdown of the MOS device.
To solve the above problems, such as short channel effects or hot electron effects, a conventional lightly doped drain (LDD) structure is provided.
FIGS. 3A-3D
are schematic, cross-sectional diagrams showing a sequential process of fabricating a conventional LDD structure. As shown in
FIG. 3A
, a polycide metal gate
34
includes polysilicon
35
and tungsten silicide
37
. The field oxide layers
33
are formed beside the gate
34
. The first light implanting is performed on the substrate using the gate
34
as a mask to form an N
−
region.
As shown in
FIG. 3B
, a layer
36
of silicon oxide (SiO
2
) or silicon nitride (Si
3
N
4
) is formed on the gate
34
and the substrate. As shown in
FIG. 3C
, an anisotropic etching step is performed on the layer
36
to form spacers
38
on the sidewalls of the gate
34
. As shown in
FIG. 3D
, the second heavy implanting is performed on the substrate using the gate
34
and the spacer
38
as masks to form an N
+
region
40
. The N
−
region and the N
+
region
40
are combined to form LDD source/drain regions.
The drawbacks of the spacer
38
of silicon oxide (SiO
2
) or silicon nitride (Si
3
N
4
) are described as follows in two conventional processes.
FIGS. 4A-4D
are schematic, sequential cross-sectional diagrams showing a self-aligned silicide (Salicide) process. As shown in
FIG. 4A
, a gate
42
and a spacer
44
are provided. As shown in
FIG. 4B
, a Ti layer
46
that is about 100-200 Å thick is formed over the wafer by magnetron DC sputtering. An annealing step is performed on the Ti layer
46
to let Ti react with silicon on the surface of the gate
42
and source/drain regions to form TiSi
2
layer
48
, as shown in
FIG. 4C. A
wet etching step is performed to remove the remaining Ti layer
46
to expose the TiSi
2
layer
48
, as shown in FIG.
4
D. During the annealing step, the TiSi
2
layer
48
sometimes forms on the spacer
44
, because the spacer
44
of silicon oxide or silicon nitride also contains silicon. The TiSi
2
layer
48
formed on the spacer
44
can be an electrical bridge between the gate
42
and source/drain regions. Therefore, the spacer
44
cannot isolate the gate
42
and source/drain regions resulting in the MOS device's failure and a decrease in the MOS device fabrication yield.
FIGS. 5A-5B
are schematic, sequential cross-sectional diagrams showing a self-aligned contact etching process. As shown in
FIG. 5A
, a gate
52
, a spacer
54
and an LDD source/drain region
56
are provided. As shown in
FIG. 5B
, a dielectric layer
58
is deposited over the whole wafer. The material of the dielectric layer
58
is silicon oxide. An etching step and a depositing step are performed on the dielectric layer
58
to form a contact
60
to electrically connect one of the LDD source/drain regions
56
. During the process of etching the dielectric layer
58
, part of the spacer
54
is removed by etching. The erosion of the spacer
54
is especially serious for the silicon oxide spacer
54
. Therefore, the gate
52
and the contact
60
are short because of the erosion of the spacer
54
and results in the MOS device's failure.
In light of the foregoing, there is a need to provide a method of fabrication an improved spacer structure.
SUMMARY OF THE INVENTION
Accordingly, the object of the present invention is to provide a method of fabricating an improved spacer. A PNO spacer is used instead of conventional silicon nitride spacer or silicon oxide spacer to improve the isolation between gate and other device structures.
Another object of the present invention is to provide a method of fabricating a PNO spacer that does not contain any silicon to avoid the TiSi
2
layer formed on the PNO spacer during Salicide process.
The other object of the present invention is to provide a method of fabricating a PNO spacer that is strong enough to avoid erosion during the process of etching a dielectric layer.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of fabricating an improved spacer. A semiconductor substrate is provided. A conductive layer, such as a gate, is formed on the semiconductor substrate and patterned to expose the semiconductor substrate. The gate structure includes a gate oxide layer formed on the semiconductor substrate and a polycide metal layer formed on the gate oxide layer. The polycide metal layer includes a polysilicon layer formed on the gate oxide layer and a tungsten silicide layer formed on the polysil

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