Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-06-07
2001-01-30
Chaudhuri, Olik (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S200000, C438S210000, C438S238000
Reexamination Certificate
active
06180462
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a method of fabricating an electronic discharge (ESD) protection device, and more particularly to a process of forming a non-silicide ESD device.
(2) Description of the Related Art
Electrostatic discharge (ESD) devices exists when a quite large voltage usually generated by suddenly is released triboelectricity (electricity caused when two materials are rubbed together). For example, a person taking an integrated circuit from its plastic wrapping material or walking across a room can generate voltage up to 2000V. Such an unintended discharge getting into a metal oxide semiconductor field effect transistor (MOSFET) can cause immediately huge damage to the circuit or subsequent early life failure. ESD devices will not work if the circuit is exposed under the normal control voltage. ESD devices will turn on to prevent the circuit from huge damage, only when the voltage is higher than the normal control voltage.
In recent years, the sizes of the individual semiconductor devices have continuously decreased so that the integrated circuit density on chips has dramatically increased. As the sizes of the capacitors become smaller, so as the resistance values of the MOS transistors are increasing, the operational speed of the IC devices is reduced, causing the performance problem. Therefore, so-called salicide process has been developed to reduce the resistance of the MOS transistors. Unfortunately, the salicide process will reduce the capacity of the ESD protection circuit, too.
In order to solve such problem, an ESD protection circuit without salicide that is incorporated with MOS transistors with salicide is proposed. Referring to FIGS.
1
A~
1
D a conventional fabrication method of an ESD protection circuit without salicide formation is depicted. An oxide layer should be formed on the ESD devices to form the non-silicide ESD devices and an dielectric layer also should be formed by depositing an oxide layer under the top capacitor electrode. As mentioned above, the process of deposition oxide layer is used twice in the conventional fabrication method of an ESD protection circuit.
Referring now to
FIG. 1A
, the conventional fabrication method of an ESD protection circuit without silicide formation is depicted. A silicon substrate
10
with a layer of gate oxide and a layer of field oxide
20
is provided. A first doped polysilicon layer is formed on the substrate
10
. After that, a layer of gate oxide and a first doped polysilicon layer are defined to form a gate oxide layer
60
and gate structures
50
at the ESD areas A, a gate oxide layer
61
and resistors
51
at resistance areas B, a gate oxide layer
62
and gate electrodes
52
at active areas C and a dielectric layer
63
and end capacitor electrodes
53
at capacitor areas D. Then, Sidewall spacers
70
are formed at the sidewall of the gate structures
50
, the resistors
51
, the gate electrodes
52
and the end capacitor electrodes
53
. Next, a process of ion implantation is performed to form the lightly doped source/drain
40
regions (LDD) and doped areas
30
.
Next, please refer to
FIG. 1A
again, a first layer of oxide
100
on the substrate
10
and a doped polysilicon layer are formed. After defining the top capacitor electrodes
90
at the capacitor areas C, the residual first layer of oxide
100
a
is patterned to form the dielectric layer between the top capacitor electrodes and the end capacitor electrodes, as shown in FIG.
1
B.
Next, refer to
FIG. 1C
, a second oxide layer
110
is formed at the ESD areas, resistance areas B and capacitor areas D. The second oxide
110
of active areas C is removed for the following salicide process on the gate electrodes
52
, source/drain regions
40
of the active areas C. The second oxide layer
110
is formed on the ESD areas A to prevent the salicidation. Finally, as shown in
FIG. 1D
, the silicide layer
81
is formed on the gate electrodes
52
and source/drain regions
40
.
As mentioned above, in accordance with the prior art, two oxide layers (first oxide layer
100
and second oxide layer
110
) should be formed. The first oxide layer
100
is deposited to form the dielectric layer
100
a
between the end capacitor electrodes
53
and top capacitor electrodes
90
. The second oxide layer
110
is deposited to form the isolation during the salicide process.
SUMMARY OF THE INVENTION
According, it is a primary object of the present invention to provide a method of fabricating an ESD protection circuit without salicide formation for integrated circuit devices with the advantages of simplifying process, reducing costs, and improving throughput.
It is another object of the present invention to provide a method of fabricating an ESD protection circuit without salicide formation for integrated circuit devices with the advantage of just forming one oxide layer.
It is yet another object of the present invention to provide a method of fabricating an ESD protection circuit with low voltage coefficient of capacitance that remains the better linear relation between the voltage and the capacitance.
These objects are accomplished by the fabrication process described below. First, the isolation regions, the dielectric layer, the gate structures, the resistors, the end capacitor electrodes and the doped regions are formed on the substrate. Next, the ESD areas and the capacitor areas are defined as the non-photolithography areas (i.e., non-photoresist). Next, ion implantation is performed in the ESD areas and the capacitor areas. Next, an oxide layer is formed on the sidewall spacers of the gate structures, the resistors, and the end capacitor electrodes. Next, an oxide layer is formed over entire semiconductor substrate. Next, the oxide layer at the active areas is removed and than salicide process is performed. Finally, the doped polysilicon layer is performed to form the top capacitor electrode.
REFERENCES:
patent: 3679942 (1972-07-01), Daly
patent: 5432129 (1995-07-01), Hodges
patent: 5516717 (1996-05-01), Hsu
patent: 5585299 (1996-12-01), Hsu
patent: 5736421 (1998-04-01), Shimomura et al.
patent: 5897348 (1999-04-01), Wu
patent: 6008077 (1999-12-01), Maeda
Chaudhuri Olik
Pham Hoai
United Microelectronics Corp.
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