Method of fabricating a trench capacitor of a memory cell

Details Method of fabricating a trench capacitor of a memory cell Method of fabricating a trench capacitor of a memory cell

2002-02-07

2003-05-20

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S249000, C438S392000

Reexamination Certificate

active

06566192

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device and, more particularly, to a method of fabrication of a trench capacitor of a memory cell.
2. Description of the Related Art
A dynamic random access memory (DRAM) cell includes a metal-oxide-semiconductor field effect transistor (MOSFET) and a capacitor that are built in a semiconductor silicon substrate. There is an electrical contact between the drain of a MOSFET and the bottom storage electrode of the adjacent capacitor to form a memory cell of the DRAM device.
In recent years, the sizes of the MOSFETs have shrunk to increase the packing densities of DRAM devices. For example, new techniques for manufacturing extremely small capacitors have been developed for 1 Giga bit DRAMs and beyond. One of the methods of increasing integration is to form a very deep trench capacitor structure, instead of the commonly used stack capacitor.
In
FIG. 1A
, a semiconductor substrate
100
is provided. A pad oxide layer
102
with thickness of about 200 angstroms is formed on the substrate
100
by oxidation. Subsequently, a pad nitride layer
106
with thickness of about 1600 angstroms is formed on the pad oxide
102
by low-pressure chemical vapor deposition (LPCVD). The pad oxide
102
and the pad nitride
104
constitute the pad layer
107
. A first masking layer
108
such as boron-silicate glass (BSG) with thickness of 5000 angstroms is formed on the pad layer
107
by CVD.
In
FIG. 1B
, the first masking layer
108
is defined and as a mask to dry etch the pad layer
107
and the substrate
100
to form a deep trench
112
with depth of about 6 micron meters. Subsequently, the pad layer
107
is used as a stop layer to remove the first masking layer
108
by isotropic etching.
In
FIG. 1C
, a doped insulating layer
120
such as an arsenic-silicate glass (ASG) with thickness of 50 to 400 angstroms conformably covers the pad layer
107
and the sidewall and the bottom of the deep trench
112
by in-situ arsenic doped LPCVD. Subsequently, a first photoresist (PR) layer (not shown) is filled into the deep trench
112
. The upper portion of the first photoresist layer is removed by PR stripping, and the remaining first photoresist layer is represented as the residual first photoresist layer
125
′.
In
FIG. 1D
, the doped insulating layer
120
on the pad layer
107
and above the residual first photoresist layer
125
′ in the deep trench
112
is removed by isotropic etching, and the remaining doped insulating layer
120
is represented as a residual doped insulating layer
120
′. Thereafter, the residual first photoresist layer
125
′ is removed. An insulating layer
128
such as tetraethyl orthosilicate (TEOS) oxide with thickness of 50 to 500 angstroms conformably covers the pad layer
107
, sidewall of the deep trench
112
and surface of the residual doped insulating layer
120
′ by LPCVD.
In
FIG. 1E
, after a drive-in process is performed, the arsenic ions in the residual doped insulating
120
′ are driven into the substrate
100
to form a junction with depth of about 800 angstroms as a bottom electrode
130
. Afterwards, the insulating layer
128
and the residual doped insulating layer
120
′ are removed. A dielectric layer
140
is formed on the surface of the bottom electrode
130
, and a conductive layer (not shown) such as a polycrystalline silicon in-situ doped with arsenic ions or phosphorus ions is then fully filled in the deep trench
112
. A portion of the conductive layer in the deep trench
112
is removed, and a portion of the conductive layer surrounded by the dielectric layer
140
remains to form a top electrode
150
. Accordingly, the manufacture of the trench capacitor of a memory cell is completed.
In
FIG. 1F
, the substrate
100
is bombarded by plasma to form the deep trench
112
during the anisotropic etching. Many sidewall pockets
160
are formed on the sidewall of the deep trench
112
because of the dislocation of crystals on the sidewall of the deep trench
112
during the bombardment process. Sidewall pockets
160
easily give rise to current leakage. In addition, since the packing density of the DRAM device is increased and the size of the MOSFET is shrunk, the current leakage of the DRAM device caused by sidewall pockets
160
cannot be ignored. Therefore, it is very important to improve the sidewall pockets in the manufacturing processes to reduce current leakage for DRAM devices.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a method of fabricating a trench capacitor of a semiconductor memory device to prevent current leakage from the capacitor.
Before forming a trench capacitor, a deep trench is formed by anisotropic etching. During the etching, the plasma bombards the sidewall of the deep trench. Many sidewall pockets are formed on the sidewall of the deep trench because of the dislocation on the exposed surface of the substrate. These sidewall packets give rise to current leakages and subsequent DRAM device failure. According to this invention, a new method of fabricating a trench capacitor of a semiconductor memory device can prevent the formation of the sidewall pockets to avoid the current leakage.
In order to achieve the above object, the method of the present invention for fabricating a trench capacitor includes the following steps. At first, a semiconductor substrate with a surface covered by a pad layer is provided. A trench is formed in the substrate. A first insulating layer is conformably formed on the pad layer and the surface of the trench. A portion of the first insulating layer is then removed to form a residual first insulating layer, wherein the upper surface of the residual first insulating layer is lower than that of the substrate. A non-doped layer is conformably formed on the pad layer, the exposed surface of the substrate and the surface of the residual first insulating layer. A portion of the non-doped layer is then removed to form a residual non-doped layer, wherein the upper surface of the residual non-doped layer is between the upper surfaces of the residual first insulating layer and the substrate. A doped insulating layer is conformably formed on the pad layer, the exposed surface of the substrate and the surface of the residual non-doped layer. A portion of the doped insulating layer is then removed to form a residual doped insulating layer, wherein the upper surface of the residual doped insulating layer is substantially level with that of the residual non-doped layer and the substrate. A second insulating layer is conformably formed on the pad layer, the exposed surfaces of the substrate and the residual non-doped layer and the surface of the residual doped layer. A drive-in process is performed to drive the ions in the residual doped insulating layer into the residual non-doped layer to form a bottom electrode. The residual doped insulating layer and the second insulating are then removed in sequence. A dielectric layer is conformably formed on the sidewall and bottom of the bottom electrode. A conductive layer is then formed on the pad layer and in the trench. Finally, a portion of the conductive layer is removed to form a top electrode, wherein the upper surface of the top electrode is substantially level with that of the dielectric layer. In addition, the first insulating layer is oxide silicon formed by LPCVD.


REFERENCES:
patent: 5380674 (1995-01-01), Kimura et al.
patent: 6096598 (2000-08-01), Furukawa et al.
patent: 6297086 (2001-10-01), Hegde et al.
patent: 6316310 (2001-11-01), Wensley et al.
patent: 6365485 (2002-04-01), Shiao et al.
patent: 6426254 (2002-07-01), Kudelka et al.

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