Method of fabricating a trench capacitor

Details Method of fabricating a trench capacitor Method of fabricating a trench capacitor

1999-07-12

2001-11-06

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S243000, C438S246000

Reexamination Certificate

active

06312982

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method of fabricating the same and, more particularly, to a memory cell transistor structure suitable for a logic/DRAM hybrid device and a method of fabricating the same.
Recently, to realize high-speed, large-amount data transfer with respect to memories, a technique capable of forming both a logic circuit and a DRAM on one chip is being required. In a logic circuit device, a technique which reduces the resistance by adhering metal silicide to a gate electrode and source and drain diffusion layers of a MOS transistor is conventionally used to improve the circuit performance. Accordingly, it is desirable to apply a similar resistance reducing technique to a DRAM cell in a logic/DRAM hybrid device.
In a DRAM cell, however, it is presumably better not to adhere metal silicide to source and drain regions in order to suppress a leakage current in a junction connecting to a memory capacitor and thereby improve the charge holding characteristic (e.g., “Trade-offs in the Integration of High Performance Devices with Trench Capacitor DRAM”, S. Crowder et al., pp. 45-48, IEDM971). One reason is that when a metal silicide film is formed on the surfaces of source and drain regions, this metal silicide may penetrate through diffusion layers to cause junction leakage. Also, forming a metal silicide film requires the formation of a heavily doped impurity diffusion layer having a dose of about 1E15/cm
2
or more in source and drain regions. When such a heavily doped impurity diffusion layer is formed, junction leakage increases due to this heavily doped impurity diffusion layer.
In the fabrication of a logic/DRAM hybrid device, it is important to reduce the number of fabrication steps. Therefore, it is required to develop a logic/DRAM hybrid device fabrication technique which simplifies the fabrication process, reduces the resistance of source and drain diffusion layers and a gate electrode, and retains the charge holding characteristic of a memory capacitor.
If regions are separated in one chip such that metal silicide is adhered in a logic circuit and is not adhered in a DRAM cell array, it is necessary to add a mask step and an accompanying processing step. This increases the number of fabrication steps.
SUMMARY OF THE INVENTION
The present invention has been made in consideration of the above situation, and has as its object to provide a semiconductor device which neither deteriorates the signal holding characteristic of an impurity diffusion layer serving as a signal storage node nor increases the number of fabrication steps, and a method of fabricating the same.
The present invention is a semiconductor device comprising a first MOS transistor having a gate electrode, and first and second impurity diffusion layers aligned with said gate electrode, in which a signal storage node capable of floating is connected to said first impurity diffusion layer, and a metal silicide film is formed on a surface of said second impurity diffusion layer, and a second MOS transistor having a gate electrode, and first and second impurity diffusion layers aligned with said gate electrode, in which a metal silicide film is formed on surfaces of both said first and second impurity diffusion layer.
The present invention is a semiconductor device comprising a semiconductor substrate and memory cells arrayed on a semiconductor substrate, said memory cells having a capacitor, and a MOS transistor having a gate electrode connected to a word line, and first and second impurity diffusion layers aligned with said gate electrode, in which said capacitor is connected to said first impurity diffusion layer, and a metal silicide film is formed on a surface of said second impurity diffusion layer.
A metal silicide film is desirably formed on the gate electrode of the MOS transistor.
The metal silicide film formed on the surface of the second impurity diffusion layer of the MOS transistor is desirably self-aligned with a region of the second impurity diffusion layer regardless of a size and position of a contact portion of the bit line.
More specifically, the device further comprises a first spacer insulating film formed on a side wall of said gate electrode on a side of said first impurity diffusion layer, in which said first spacer insulating film connects to a spacer insulating film of an adjacent gate electrode on the side of said first impurity diffusion layer so as to cover consecutively said first impurity diffusion layer, and a second spacer insulating film formed on a side wall of said gate electrode on a side of said second impurity diffusion layer, in which said second spacer insulating film is separated by a predetermined interval from a spacer insulating film of an adjacent gate electrode on the side of said second impurity diffusion layer so as to make said metal silicide film formed on the surface of said second impurity diffusion layer in a state of being aligned with the predetermined interval.
A logic circuit having a plurality of MOS transistors is desirably integrated on the semiconductor substrate, and a metal silicide film is desirably formed by self-alignment on surfaces of source and drain diffusion layers and gate electrode of each MOS transistor constructing the logic circuit.
A method of fabricating a semiconductor device according to the present invention comprises the steps of forming a capacitor on a semiconductor substrate, forming a MOS transistor having a gate electrode serving as a word line and first and second impurity diffusion layers aligned with the gate electrode, the first impurity diffusion layer being connected to one node of the capacitor, forming a metal silicide film on a surface of the second impurity diffusion layer of the MOS transistor, and forming a bit line connected to the second impurity diffusion layer of the MOS transistor via the metal silicide film.
The metal silicide film is desirably self-aligned with a region of the second impurity diffusion layer and the gate electrode of the MOS transistor.
The method further comprises, before the step of forming the metal silicide film, the step of forming first and second spacer insulating films on side walls of the gate electrode of the MOS transistor on the sides of the first and second impurity diffusion layers, respectively, such that the first spacer insulating film connects to a spacer insulating film of an adjacent gate electrode on the side of the first impurity diffusion layer to cover the first impurity diffusion layer, and the second spacer insulating film on the side of the second impurity diffusion layer is separated by a predetermined interval from a spacer insulating film of an adjacent gate electrode on the side of the second impurity diffusion layer to thereby expose the second impurity diffusion layer.
In the present invention, of the first and second impurity diffusion layers of the MOS transistor, a metal silicide film is not formed on the first impurity diffusion layer connected to the signal storage node and is formed only on the second impurity diffusion layer. Accordingly, it is possible to well maintain the signal holding characteristic of the signal storage node and reduce the resistance of the impurity diffusion layer.
Especially when the present invention is applied to a DRAM, it is possible to prevent deterioration of the charge holding characteristic caused by junction leakage on the side of a capacitor of a DRAM memory cell and reduce the resistance of an impurity diffusion layer on the side of a bit line contact.
In the present invention, a metal silicide film can be formed only on the second impurity diffusion layer of the first and second impurity diffusion layers of the MOS transistor without using any special mask step. This is accomplished by optimally designing the pattern and size of gate electrodes serving as word lines and forming a portion in which a spacer insulating film formed on the side walls of the gate electrodes completely fills the interval between the gate electrodes and a portion in w

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