Method of fabricating a transistor

Details Method of fabricating a transistor Method of fabricating a transistor

1999-08-10

2001-07-17

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S302000, C438S305000

Reexamination Certificate

active

06261912

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor fabrication method. More particularly, the present invention relates to a method of fabricating a transistor.
2. Description of the Related Art
Conventionally, a self-aligned silicide layer, also known as a salicide layer, is formed on a source/drain region, which is located on opposite sides of a gate, so as to decrease the resistance for a transistor.
FIGS. 1A through 1F
are schematic, cross-sectional views illustrating a conventional method of fabricating a transistor.
In
FIG. 1A
, a gate
106
is formed on a substrate
100
. The gate
106
comprises a gate oxide layer
102
and a polysilicon layer
104
formed in sequence over the substrate
100
. A shallow trench isolation (STI) structure
108
is formed in a portion of the substrate
100
.
In
FIG. 1B
, a light doping step is performed with the gate
106
serving as a mask. A lightly doped drain (LDD) region
110
, which has a pocket-doped region, is formed in the substrate
100
on opposite sides of the gate
106
.
In
FIG. 1C
, an oxide layer (not shown) is formed by chemical vapor deposition over the substrate
100
to cover the gate
106
. Anisotropic etching is performed to etch the oxide layer. A spacer
112
is formed on a sidewall of the gate
106
.
In
FIG. 1D
, a doping step is performed with the gate
106
and the spacer
112
serving as masks. Arsenic (As) ions are doped into the substrate
100
. The arsenic-doping step is performed with a high energy of about 60-80 KeV and a high dosage of about 3E15 atoms/cm
2
. A source/drain region
114
is formed in the substrate
100
on opposite sides of the spacer
112
.
In
FIG. 1E
, a titanium layer
116
having a thickness of about 200 angstroms to about 1000 angstroms is formed over the substrate
100
by sputtering.
In
FIG. 1F
, a thermal step is performed. During the thermal step, the titanium layer
116
reacts with the silicon of the gate
106
and the source/drain region
114
to form silicide layers
118
, known as self-aligned silicide layers. A wet etching is performed with a H
2
O
2
solution and a NH
4
OH solution to remove the unreacted titanium layer
116
.
In the above-described fabrication process, the source/drain region
114
is formed by doping the arsenic (As) ions with a high energy of about 60-80 KeV and a high dosage of about 3E15 atoms/cm
2
. During the high-energy ion bombardment, dislocations are easily formed in the substrate
100
and affect the device performance. In contrast, if the source/drain region
114
is formed by doping arsenic ions having a low energy and a high dosage, dislocations in the substrate
100
can be reduced. However, even though the dislocations can be reduced in this manner, the formation of the silicide layer is partially obstructed by the high-concentration source/drain region
114
. This, in turn, decreases the formation of the silicide layer, resulting in an increased resistance. In addition, the drain-induced barrier lowering (DIBL) effect can be reduced by an LDD structure formed with a low doping energy. However, in order to increase the saturated current (I
DSAT
) of devices, dosages are increased. In this manner, the resistance for source/drain region
114
is affected.
Moreover, since the thermal step for forming the silicide layer
118
is performed after the formation of the source/drain region
114
. In the high-temperature environment, ions in the source/drain region
114
tend to further diffuse. As a result, junction capacitance of the source/drain region
114
is increased, and thus the operation speed is affected. The junction leakage current is increased.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating a transistor. A gate structure is formed on a substrate. A spacer is formed on a sidewall of the gate structure. A first doping step is performed with the gate structure and the spacer serving as masks to form a source/drain region in the substrate. A silicide layer is formed on the source/drain region. The spacer is removed. A second doping step is performed with the gate structure serving as a mask to form a lightly doped drain region in the substrate.
Preferably, dopant ions in the first doping step comprise phosphorus (P) ions. The first doping step is preferably performed with an energy of about 40-50 KeV and most preferably about 50 KeV. The first doping step is preferably performed with a dosage of about 1E13-6E13 atoms/cm
2
and most preferably about 3E13 atoms/cm
2
.
Preferably, dopant ions in the second doping step comprise arsenic ions. The second doping step is preferably performed with an energy of about 5-10 KeV. The second doping step is preferably performed with a dosage of about 1E15-3E15 atoms/cm
2
and most preferably about 3E15 atoms/cm
2
.
The present invention forms the source/drain region by doping phosphorus ions having a low doping energy of about 40-50 KeV. This is in order to prevent dislocations from forming in the substrate, prevent junction leakage current, and improve junction capacitance.
Moreover, the invention forms the silicide layer before the lightly doped drain region is formed. In this manner, the light doping step for forming the lightly doped drain region is performed without decreasing the formation of the silicide layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5472890 (1995-12-01), Oda
patent: 5491099 (1996-02-01), Hsu
patent: 5635417 (1997-06-01), Natsume
patent: 5705414 (1998-01-01), Lustig
patent: 5783457 (1998-07-01), Hsu
patent: 5834355 (1998-11-01), Doyle
patent: 5899719 (1999-05-01), Hong

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