Method of fabricating a test pattern for junction leakage...

Details Method of fabricating a test pattern for junction leakage... Method of fabricating a test pattern for junction leakage...

2006-07-11

2006-07-11

Smith, Bradley K. (Department: 2891)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S017000, C438S583000, C438S682000

Reexamination Certificate

active

07074711

ABSTRACT:
A method of forming a salicide pattern for measuring junction leakage current is disclosed. An example method forms device isolation structures on a silicon substrate, forms a well region between the device isolation structures, forms source and drain regions on the well region, and forms a salicide layer on the source and drain regions. The example method also removes some part of the salicide layer, deposits an interlayer dielectric layer on the salicide layer, and forms via holes in the interlayer dielectric layer and filling metal into the via holes to form a via. The example method further planarizes the interlayer dielectric layer and the via, and forms metal interconnects on the interlayer dielectric layer.

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patent: 6350636 (2002-02-01), Lee et al.
S. Wolf, Silicon Processing for the VLSI Era, 1990, vol. 2, p. 154.

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