Method of fabricating a static random access memory

Details Method of fabricating a static random access memory Method of fabricating a static random access memory

2000-05-24

2001-09-11

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S282000

Reexamination Certificate

active

06287909

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89107550, filed Apr. 21, 2000.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of fabricating a static random access memory. More particularly, the present invention relates to a method of fabricating a buried contact in a static random access memory.
2. Description of Related Art
Static random access memory (SRAM) is the fastest in the family of semiconductor memory; therefore, SRAM is widely used in many applications, such as cache memory. At present SRAM is commonly applied in digital devices, including minicomputers and microprocessor systems.
The structure of SRAM is divided into memory cells and periphery circuits. The memory cell is used to store information. Periphery circuits contain address decoders that are used to decode the addresses of memory cells, and circuits that are related to memory operation.
The prior art contact structures in SRAM mostly are formed on the source/drains; however, the prior art structures are not suitable for high-integration integrated circuits. Consequently, a buried contact that is compatible with local interconnects is used for high-integration integrated circuits. The buried contact can decrease the application areas of chips; for example, twenty-five percent of the application area is saved when the buried contact is used in SRAM. Therefore, the application of buried contacts is useful for the production of high-density devices.
FIG. 1A
to
FIG. 1D
are schematic, cross-sectional views illustrating process steps of fabricating a buried contact in SRAM according to the prior art.
Referring to
FIG. 1A
, a substrate
100
is provided. A gate oxide layer
102
and a first polysilicon layer
104
are sequentially formed on the substrate
100
. Gate oxide layer
102
and the first polysilicon layer
104
are patterned and defined to form a buried contact opening
105
.
Referring to
FIG. 1B
, a second polysilicon layer
106
is formed over the substrate
100
and fills buried contact opening
105
(FIG.
1
A). A buried contact
108
is formed in the substrate
100
exposed by buried contact opening
105
.
Referring to
FIG. 1C
, a photoresist layer
110
is formed on the second polysilicon layer
106
. Photoresist layer
110
is used to define gate oxide layer
102
, first polysilicon layer
104
and second polysilicon layer
106
, thereby to form polysilicon gates. A patterned gate oxide layer
102
a
, a patterned first polysilicon layer
104
a
and a patterned second polysilicon layer
106
a
are formed thereon and a part of the surface of substrate
100
is exposed, in which a source/drain
116
(
FIG. 1D
) is to be formed. Before defining, buried contact
108
is covered by only one polysilicon layer
106
, but the non-buried-contact region in the substrate
100
is covered by two polysilicon layers
104
,
106
. Moreover, the material of substrate
100
is similar to the material of the second polysilicon layer
106
. When a part of the polysilicon layer
106
above buried contact
108
is etched during the definition process for gate oxide layer
102
, first polysilicon layer
104
and second polysilicon layer
106
, it is easy to over-etch a part of substrate
100
inside the buried contact
108
and form a silicon trench
114
thereon in the buried contact
108
. Silicon trench
114
causes current leakage. As silicon trench
114
becomes larger, it cuts through buried contact
108
(as illustrated in
FIG. 1C
) and causes open circuits between buried contact
108
and source/drain
116
that is to be formed later.
Referring to
FIG. 1D
, after photoresist layer
110
is removed, source/drain
116
is formed in the substrate
100
when patterned gate oxide layer
102
a
, patterned first polysilicon layer
104
a
and patterned second polysilicon layer
106
a
are used as a mask for ion implantation.
In the prior art, a part of substrate
100
inside buried contact
108
is over-etched to form silicon trench
114
when a part of polysilicon layer
106
is removed because only one polysilicon layer
106
covers buried contact
108
. As the depth of silicon trench
114
increases the contact area between source/drain
116
and buried contact
108
in the substrate
100
decreases, which further increases resistivity. If silicon trench
114
is too deep, the current flowing from buried contact
108
through source/drain
116
reorients to be grounded through the substrate
100
, which causes junction leakage.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating a buried contact in a SRAM. As embodied and broadly described herein, a substrate is provided and a gate oxide layer, a first conducting layer and a masking layer are formed sequentially on the substrate. A buried contact opening is formed inside the gate oxide layer, the first conducting layer and the masking layer, which opening exposes a part of the substrate. An epitaxial layer is formed inside the buried contact opening, which epitaxial layer fills up the buried contact opening. After the masking layer is removed, a second conducting layer is formed above the substrate. A buried contact is formed in the substrate that is below the epitaxial layer. The gate oxide layer, the first conducting layer, the epitaxial layer and second conducting layer are patterned to expose a part of the substrate and a part of the buried contact. A source/drain is formed in the substrate and a part of the source/drain is mixed with a part of the buried contact, while patterned gate oxide layer, patterned first conducting layer, patterned epitaxial layer and patterned second conducting layer are used as a mask.
The combined thickness of the epitaxial layer and the second conducting layer above the buried contact is the same as the combined thickness of the gate oxide layer, the first conducting layer and the second conducting layer. Because the buried contact is covered by more than one conducting layer, the substrate inside the buried contact is not over-etched to cause silicon trench problems during the definition process for the gate oxide layer, the first conducting layer and the second conducting layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5998269 (1999-12-01), Huang et al.

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